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Volumn , Issue , 2007, Pages 337-340

A 57dB SFDR digitally calibrated 500MS/s folding ADC in 0.18μm digital CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; SIGNAL PROCESSING; TRANSISTORS;

EID: 39549098413     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405747     Document Type: Conference Paper
Times cited : (4)

References (4)
  • 1
    • 10444248089 scopus 로고    scopus 로고
    • R.C. Taft, C.A.. Menkus, M.R. Tursi, O. Hidri and V. Pons, A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency, IEEE J. Solid-State Circuits, 39, Issue 12, Dec. 2004 Page(s):2107-2115
    • R.C. Taft, C.A.. Menkus, M.R. Tursi, O. Hidri and V. Pons, "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency", IEEE J. Solid-State Circuits, Vol. 39, Issue 12, Dec. 2004 Page(s):2107-2115
  • 2
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec Pages
    • B. Murmann and B.E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE J. Solid-State Circuits, Vol. 38, Issue 12, Dec 2003 Page(s):2040 - 2050
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.12 , pp. 2040-2050
    • Murmann, B.1    Boser, B.E.2
  • 3
    • 0036503232 scopus 로고    scopus 로고
    • A 'digital' 6-bit ADC in 0.25μm CMOS
    • March Pages
    • C. Donovan and M.P. Flynn, "A 'digital' 6-bit ADC in 0.25μm CMOS", IEEE J. Solid-State Circuits, Vol. 37, Issue 3, March 2002 Page(s): 432-437
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.3 , pp. 432-437
    • Donovan, C.1    Flynn, M.P.2
  • 4
    • 0030411456 scopus 로고    scopus 로고
    • An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
    • Dec, Pages
    • A.G.W. Venes and R.J. van-de-Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing", IEEE J. Solid-State Circuits, Vol. 31, Issue 12, Dec. 1996 Page(s):1846- 1853
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.12 , pp. 1846-1853
    • Venes, A.G.W.1    van-de-Plassche, R.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.