메뉴 건너뛰기




Volumn , Issue , 2008, Pages 9-12

Mismatch analysis and statistical design at 65 nm and below

Author keywords

Input offset voltage; Mismatch model; Sense amplifier

Indexed keywords

GAS DYNAMIC LASERS; STATIC RANDOM ACCESS STORAGE;

EID: 57849135551     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672006     Document Type: Conference Paper
Times cited : (28)

References (7)
  • 2
    • 3042566937 scopus 로고    scopus 로고
    • An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs
    • June
    • R. Singh and N. Bhat, "An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs," VLSI Systems, IEEE Transactions on, vol. 12, pp. 652-657, June 2004.
    • (2004) VLSI Systems, IEEE Transactions on , vol.12 , pp. 652-657
    • Singh, R.1    Bhat, N.2
  • 4
    • 0034246928 scopus 로고    scopus 로고
    • Yield and matching implications for static RAM memory array sense-amplifier design
    • August
    • S.J. Lovett, G.A. Gibbs, and A. Pancholy, "Yield and matching implications for static RAM memory array sense-amplifier design," IEEE J. of Solid-State Circuits, vol. 35, pp. 1200-1204, August 2000.
    • (2000) IEEE J. of Solid-State Circuits , vol.35 , pp. 1200-1204
    • Lovett, S.J.1    Gibbs, G.A.2    Pancholy, A.3
  • 5
    • 3042778488 scopus 로고    scopus 로고
    • Yield and optimization of a latch type voltage sense amplifier
    • July
    • B. Wicht, T. Nirschl, and D. Schmitt-Lansiedel, "Yield and optimization of a latch type voltage sense amplifier," IEEE J. of Solid-State Circuits, vol. 39, pp. 1148-1158, July 2004.
    • (2004) IEEE J. of Solid-State Circuits , vol.39 , pp. 1148-1158
    • Wicht, B.1    Nirschl, T.2    Schmitt-Lansiedel, D.3
  • 6
    • 12344265531 scopus 로고    scopus 로고
    • On-chip wires: Scaling and efficiency,
    • Ph.D. Thesis, Stanford University
    • R. Ho, "On-chip wires: Scaling and efficiency," Ph.D. Thesis, Stanford University, 2003.
    • (2003)
    • Ho, R.1
  • 7
    • 50249184105 scopus 로고    scopus 로고
    • Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization
    • X. Li, B. Taylor, Y-T. Chien, L. Pileggi, "Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization," ICCAD, 2007.
    • (2007) ICCAD
    • Li, X.1    Taylor, B.2    Chien, Y.-T.3    Pileggi, L.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.