A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 7, 2005, Pages 1499-1504

  Sandner, Christoph ^a   Clara, Martin ^a   Santner, Andreas ^a   Hartig, Thomas ^a   Kuttner, Franz ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

Capacitive interpolation; Data converter; Flash ADC; Sampling

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CAPACITORS; COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; HARD DISK STORAGE; INTERPOLATION; OPTIMIZATION; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

CAPACITIVE INTERPOLATION; DATA CONVERTERS; FLASH ADC; SAMPLING CAPACITORS;

CMOS INTEGRATED CIRCUITS;

EID: 22544471871     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.847215     Document Type: Conference Paper

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