A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 2, 2005, Pages 532-535

  Jiang, Xicheng ^a,b   Chang, Mau Chung Frank ^a  

^a University of California   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

Analog to digital converter (ADC); Averaging; CMOS; Interleaving; Track hold; Triple cross connection

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; DATA COMMUNICATION SYSTEMS; NYQUIST DIAGRAMS; POWER AMPLIFIERS; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO; TELECOMMUNICATION LINKS;

ANALOG-TO-DIGITAL CONVERTER (ADC); AVERAGING; CMOS; INTERLEAVING; TRACK/HOLD; TRIPLE-CROSS CONNECTION;

CMOS INTEGRATED CIRCUITS;

EID: 13444283710     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.841033     Document Type: Article

References (9)

1. K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash A/D converters," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1991, pp. 170-171.
2. 2," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1887-1895, Dec. 1997.
3. M. Choi and A. A. Abidi, "A 6 b 1.3 Gsample/s A/D converter in 0.35 μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001.
4. P. Scholtens and M. Vertregt, "A 6-b 1.6-Gsamples/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Dec. 2002.
5. J. White and A. Wilson Jr., "On the equivalence of spatial and temporal stability for translation invariant linear resistive networks," IEEE Trans. Circuits Syst., vol. 39, pp. 734-743, Sep. 1992.
6. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1433-1440, Oct. 1989.
7. W. Black and D. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, no. 12, pp. 1022-1029, Dec. 1980.
8. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
9. J. Doernberg, H. Lee, and D. Hodges, "Full-speed testing of A/D converter," IEEE J. Solid-State Circuits, vol. 19, no. 2, pp. 820-827, Feb. 1984.