-
1
-
-
44849118533
-
A 0.2 v 0.44 W 20 kHz analog to digital -modulator with 57 fJ/conversion FoM
-
Sep.
-
U. Wismar, D. Wisland, and P. Andreani, "A 0.2 V 0.44 W 20 kHz analog to digital -modulator with 57 fJ/conversion FoM," in Proc. ESSCIRC, Sep. 2006, pp. 187-190.
-
(2006)
Proc. ESSCIRC
, pp. 187-190
-
-
Wismar, U.1
Wisland, D.2
Andreani, P.3
-
4
-
-
0036544662
-
Speed-power-accuracy tradeoff in high-speed CMOS ADCs
-
Apr.
-
K. Uyttenhove and M. Steyaert, "Speed-power-accuracy tradeoff in high-speed CMOS ADCs," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol.49, no.4, pp. 280-287, Apr. 2002.
-
(2002)
IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process.
, vol.49
, Issue.4
, pp. 280-287
-
-
Uyttenhove, K.1
Steyaert, M.2
-
5
-
-
0021616937
-
A self-calibrating 15 bit CMOS A/D converter
-
H.-S. Lee, D. Hodges, and P. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol.19, no.6, pp. 813-819, 1984.
-
(1984)
IEEE J. Solid-State Circuits
, vol.19
, Issue.6
, pp. 813-819
-
-
Lee, H.-S.1
Hodges, D.2
Gray, P.3
-
6
-
-
63449113431
-
A low power 6-bit flash ADC with reference voltage and common-mode calibration
-
Apr.
-
C.-Y. Chen, M. Le, and K. Y. Kim, "A low power 6-bit flash ADC with reference voltage and common-mode calibration," IEEE J. Solid-State Circuits, vol.44, no.4, pp. 1041-1046, Apr. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.4
, pp. 1041-1046
-
-
Chen, C.-Y.1
Le, M.2
Kim, K.Y.3
-
7
-
-
0030286542
-
Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization
-
Nov.
-
C. Enz and G. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol.84, no.11, pp. 1584-1614, Nov. 1996.
-
(1996)
Proc. IEEE
, vol.84
, Issue.11
, pp. 1584-1614
-
-
Enz, C.1
Temes, G.2
-
8
-
-
0037946889
-
Digital calibration incorporating redundancy of flash ADCs
-
May
-
M. Flynn, C. Donovan, and L. Sattler, "Digital calibration incorporating redundancy of flash ADCs," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol.50, no.5, pp. 205-213, May 2003.
-
(2003)
IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process.
, vol.50
, Issue.5
, pp. 205-213
-
-
Flynn, M.1
Donovan, C.2
Sattler, L.3
-
9
-
-
0012486966
-
IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters
-
IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000, 2001.
-
(2001)
IEEE Std
, pp. 1241-2000
-
-
-
10
-
-
67649973977
-
A 6b stochastic flash analog-to-digital converter without calibration or reference ladder
-
S. Weaver, B. Hershberg, D. Knierim, and U.-K. Moon, "A 6b stochastic flash analog-to-digital converter without calibration or reference ladder," in Proc. IEEE Asian Solid-State Circuits Conf., 2008.
-
(2008)
Proc. IEEE Asian Solid-State Circuits Conf.
-
-
Weaver, S.1
Hershberg, B.2
Knierim, D.3
Moon, U.-K.4
-
11
-
-
29044444622
-
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators
-
G.-C. Ahn, D.-Y. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita, K. Takasuka, G. Temes, and U. Moon, "A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2398-2407, Dec. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.12
, pp. 2398-2407
-
-
Ahn, G.-C.1
Chang, D.-Y.2
Brown, M.3
Ozaki, N.4
Youra, H.5
Yamamura, K.6
Hamashita, K.7
Takasuka, K.8
Temes, G.9
Moon, U.10
-
12
-
-
0035273851
-
Very low-voltage digital-audio-modulator with 88-dB dynamic range using local switch bootstrapping
-
Mar.
-
M. Dessouky and A. Kaiser, "Very low-voltage digital-audio-modulator with 88-dB dynamic range using local switch bootstrapping," IEEE J. Solid-State Circuits, vol.36, no.3, pp. 349-355, Mar. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.3
, pp. 349-355
-
-
Dessouky, M.1
Kaiser, A.2
-
13
-
-
41549109327
-
A 0.5-V 8-bit 10-MS/s pipelined ADC in 90-nm CMOS
-
Apr.
-
J. Shen and P. R. Kinget, "A 0.5-V 8-bit 10-MS/s pipelined ADC in 90-nm CMOS," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 787-795, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 787-795
-
-
Shen, J.1
Kinget, P.R.2
-
14
-
-
51549119208
-
Low-power successive approximation converter with 0.5Vsupply in 90 nm CMOS
-
Nov.
-
S. Gambini and J. Rabaey, "Low-power successive approximation converter with 0.5Vsupply in 90 nm CMOS," IEEE J. Solid-State Circuits, vol.42, no.11, pp. 2348-2356, Nov. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.11
, pp. 2348-2356
-
-
Gambini, S.1
Rabaey, J.2
-
15
-
-
0034867611
-
Scaling of stack effect and its application for leakage reduction
-
Aug.
-
S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction," in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2001, pp. 195-200.
-
(2001)
Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED)
, pp. 195-200
-
-
Narendra, S.1
Borkar, S.2
De, V.3
Antoniadis, D.4
Chandrakasan, A.5
-
16
-
-
0028733304
-
A 200 MHz 13 mm 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme
-
Dec.
-
M. Matsui, H. Hara, Y. Uetani, L.-S. Kim, T. Nagamatsu, Y.Watanabe, A. Chiba, K. Matsuda, and T. Sakurai, "A 200 MHz 13 mm 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme," IEEE J. Solid-State Circuits, vol.29, no.12, pp. 1482-1490, Dec. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.12
, pp. 1482-1490
-
-
Matsui, M.1
Hara, H.2
Uetani, Y.3
Kim, L.-S.4
Nagamatsu, T.5
Chiba, A.6
Matsuda, K.7
Sakurai, T.8
-
18
-
-
70449491973
-
-
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, C. G. Sodini, Ed. New York: Pearson Education, Inc., 2003
-
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, C. G. Sodini, Ed. New York: Pearson Education, Inc., 2003.
-
-
-
-
19
-
-
0018056638
-
A CMOS voltage reference
-
Y. Tsividis and R. Ulmer, "A CMOS voltage reference," IEEE J. Solid- State Circuits, vol.13, no., pp. 774-778, Dec. 1978.
-
(1978)
IEEE J. Solid- State Circuits
, vol.13
, pp. 774-778
-
-
Tsividis, Y.1
Ulmer, R.2
-
20
-
-
0021586344
-
Full-speed testing of A/D converters
-
Dec.
-
J. Doernberg, H.-S. Lee, and D. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol.19, no., pp. 820-827, Dec. 1984.
-
(1984)
IEEE J. Solid-State Circuits
, vol.19
, pp. 820-827
-
-
Doernberg, J.1
Lee, H.-S.2
Hodges, D.3
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