Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

IEEE Transactions on Device and Materials Reliability

Volumn 4, Issue 3, 2004, Pages 306-319

  Gehring, Andreas ^a   Selberherr, Siegfried ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Device simulation; Gate dielectric breakdown; Nonvolatile memory reliability; Tunneling

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC DEVICES; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRON TUNNELING; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; RELIABILITY; THREE DIMENSIONAL;

DEVICE SIMULATION; GATE DIELECTRIC BREAKDOWN; NONVOLATILE MEMORY RELIABILITY; TUNNELING CURRENT;

DATA STORAGE EQUIPMENT;

EID: 11144227976     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2004.836727     Document Type: Article

References (109)

1. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proc. IEEE, vol. 91, pp. 489-502, Apr. 2003.
2. W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373, July 2001.
3. R. Tsu and L. Esaki, "Tunneling in a finite superlattice," Appl. Phys. Lett., vol. 22, no. 11, pp. 562-564, 1973.
4. S. Harasek, H. D. Wanzenböck, and E. Bertagnolli, "Compositional and electrical properties of zirconium dioxide thin films chemically deposited on silicon," J. Vac. Sci. Technol. A, vol. 21, no. 3, pp. 653-659, 2003.
5. M. Houssa, M. Tuominen, M. Naili, V. Afanas'ev, A. Stesmans, S. Haukka, and M. M. Heyns, "Trap-assisted tunneling in high permittivity gate dielectric stacks," J. Appl. Phys., vol. 87, no. 12, pp. 8615-8620, 2000.
6. 3 field-effect transistors," J. Appl. Phys., vol. 94, no. 3, pp. 1728-1737, 2003.
7. C. B. Duke, Tunneling in Solids. New York: Academic, 1969.
8. Khairurrijal, W. Mizubayashi, S. Miyazaki, and M. Hirose, "Analytic model of direct tunnel current through ultrathin gate oxides," J. Appl. Phys., vol. 87, no. 6, pp. 3000-3005, 2000.
9. M. Lundstrom and Z. Ren, "Essential physics of carrier transport in nanoscale MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 133-141, Jan. 2002.
10. D. Cassi and B. Riccó, "An analytical model of the energy distribution of hot electrons," IEEE Trans. Electron Devices, vol. 37, pp. 1514-1521, June 1990.
11. K.-I. Sonoda, M. Yamaji, K. Taniguchi, C. Hamaguchi, and S. T. Dunham, "Moment expansion approach to calculate impact ionization rate in submicron silicon devices," J. Appl. Phys., vol. 80, no. 9, pp. 5444-5448, 1996.
12. T. Grasser, H. Kosina, C. Heitzinger, and S. Selberherr, "Characterization of the hot electron distribution function using six moments," J. Appl. Phys., vol. 91, no. 6, pp. 3869-3879, 2002.
13. L. Selmi, A. Ghetti, R. Bez, and E. Sangiorgi, "Trade-offs between tunneling and hot-carrier injection in short channel floating gate MOSFETs," Microelectron. Eng., vol. 36, no. 1-4, pp. 293-296, 1997.
14. T. Grasser, H. Kosina, and S. Selberherr, "An impact ionization model including non-Maxwellian and nonparabolicity effects," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2001, pp. 46-49.
15. _, "Influence of the distribution function shape and the band structure on impact ionization modeling," J. Appl. Phys., vol. 90, no. 12, pp. 6165-6171, 2001.
16. A. Abramo and C. Fiegna, "Electron energy distributions in silicon structures at low applied voltages and high electric fields," J. Appl. Phys., vol. 80, no. 2, pp. 889-893, 1996.
17. A. Gehring, T. Grasser, H. Kosina, and S. Selberherr, "Simulation of hot-electron oxide tunneling current based on a non-Maxwellian electron energy distribution function," J. Appl. Phys., vol. 92, no. 10, pp. 6019-6027, 2002.
18. _, "Energy transport gate current model accounting for non-Maxwellian energy distribution," Electron. Lett., vol. 39, no. 8, pp. 691-692, 2003.
19. K. H. Gundlach, "Zur Berechnung des Tunnelstroms durch eine trapezförmige Potentialstufe," Solid-State Electron., vol. 9, pp. 949-957, 1966.
20. B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer, "VARIOT: A novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices," IEEE Electron Device Lett., vol. 24, pp. 99-101. Feb. 2003.
21. G. Wachutka, "New layer method for the investigation of the electronic properties of two-dimensional periodic spatial structures: First applications to copper and aluminum," Phys. Rev. B, vol. 34, no. 12, pp. 8512-8527, 1986.
22. D. Y. K. Ko and J. C. Inkson, "Matrix method for tunneling in heterostructures: Resonant tunneling in multilayer systems," Phys. Rev. B, vol. 38, no. 14, pp. 9945-9951, 1988.
23. D. Z. Y. Ting, E. T. Yu, and T. C. McGill, "Multiband treatment of quantum transport in interband tunnel devices," Phys. Rev. B, vol. 45, no. 7, pp. 3583-3592, 1992.
24. T. Usuki, M. Saito, M. Takatsu, R. A. Kiehl, and N. Yokoyama, "Numerical analysis of ballistic-electron transport in magnetic fields by using a quantum point contact and a quantum wire," Phys. Rev. B, vol. 52, no. 11, pp. 8244-8258, 1995.
25. B. A. Biegel, "Quantum electronic device simulation," dissertation, Stanford Univ., Stanford, CA, 1997.
26. F. Heinz, "Simulation approaches for nanoscale semiconductor devices," dissertation, ETH Zürich, Switzerland, 2004.
27. C. S. Lent and D. J. Kirkner, "The quantum transmitting boundary method," J. Appl. Phys., vol. 67, no. 10, pp. 6353-6359, 1990.
28. W. R. Frensley, "Numerical evaluation of resonant states," Superlattices and Microstructures, vol. 11, no. 3, pp. 347-350, 1992.
29. U. Ravaioli, "Numerical methods for the solution of Schrödinger equation for ballistic transport," presented at the 2002 School on Computational Material Science, Univ. Illinois at Urbana-Champaign, http://www.mcc.uiuc.edu/SummerSchool02/.
30. F. Stern, "Self-consistent results for n-type Si inversion layers," Phys. Rev. B, vol. 5, no. 12, pp. 4891-4899, 1972.
31. W. Magnus and W. Schoenmaker, "On the calculation of gate tunneling currents in ultra-thin metal-insulator-semiconductor capacitors," Micro-electron. Reliabil., vol. 41, no. 1, pp. 31-35, 2001.
32. E. Cassan, "On the reduction of direct tunneling leakage through ultrathin gate oxides by a one-dimensional Schrödinger-Poisson solver," J. Appl. Phys., vol. 87, no. 11, pp. 7931-7939, 2000.
33. R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis, "Theory of direct tunneling current in metal-oxide-semiconductor structures," J. Appl. Phys., vol. 91, no. 3, pp. 1400-1409, 2002.
34. DESSIS 9.5 User's Manual, Integrated Systems Engineering (ISE), Mountain View, CA, 2004.
35. MEDICI 2002.4.0 User's Manual, Synopsys, Mountain View, CA, 2003.
36. ATLAS User's Manual, Silvaco, Santa Clara, CA, 2004.
37. A. D. Serra, A. Abramo, P. Palestri, L. Selmi, and F. Widdershoven, "Closed- and open-boundary models for gate-current calculation in n-MOSFETs," IEEE Trans. Electron Devices, vol. 48, pp. 1811-1815, Aug. 2001.
38. A. Gehring and S. Selberherr, "On the calculation of quasi-bound states and their impact on direct tunneling in CMOS devices," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2004.
39. W. Franz, Handbuch der Physik. Berlin, Germany: Springer, 1956, vol. XVII, p. 155.
40. J. Maserjian, "Tunneling in thin MOS structures," J. Vac. Sci. Technol., vol. 11, no. 6, pp. 996-1003, 1974.
41. R. Clerc, "Etude des Effets Quantiques dans les Composants CMOS a Oxydes de Grille Ultra Minces - Modelization et Caracterization," dissertation, Institut National Polytechnique de Grenoble, France, 2001.
42. 2 interfaces," J. Appl. Phys., vol. 52, no. 4, pp. 2897-2908, 1981.
43. S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs," IEEE Trans. Electron Devices, vol. 18, pp. 209-211, May 1997.
44. L. F. Register, E. Rosenbaum, and K. Yang, "Analytic model for direct tunneling current in polycristalline silicon-gate metal-oxide- semiconductor devices," Appl. Phys. Lett., vol. 74, no. 3, pp. 457-459, 1999.
45. 2," Appl. Phys. Lett., vol. 75, no. 10, pp. 1407-1409, 1999.
46. 2 gate oxides from microscopic models," J. Appl. Phys., vol. 89, no. 1, pp. 348-363, 2001.
47. 2 gate oxides in MOSFETs," Solid-State Electron., vol. 46, no. 7, pp. 1027-1032, 2002.
48. M. Städele, F. Sacconi, A. Di Carlo, and P. Lugli, "Enhancement of the effective tunnel mass in ultrathin silicon dioxide layers," J. Appl. Phys., vol. 93, no. 5, pp. 2681-2690, 2003.
49. 2," J. Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969.
50. K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-thin silicon dioxide leakage current and scaling limit," in Symp. VLSI Technol. Tech. Dig., 1992, pp. 18-19.
51. J. P. Shiely, "Simulation of tunneling in MOS devices," dissertation, Duke Univ., Durham, NC, 1999.
52. A. Gehring, "Simulation of tunneling in semiconductor devices," dissertation, Technische Universität Wien, Austria, 2003.
53. S. H. Lo, D. A. Buchanan, and Y. Taur, "Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFET's with ultrathin oxides," IBM J. Res. Dev., vol. 43, no. 3, pp. 327-337, 1999.
54. MINIMOS-NT 2.1 User's Guide, Institut für Mikroelektronik, Technische Universität Wien, Austria, 2004.
55. J. D. Casperson, L. D. Bell, and H. A. Atwater, "Materials issues for layered tunnel barrier structures," J. Appl. Phys., vol. 92, no. 1, pp. 261-267, 2002.
56. F. Capasso, F. Beltram, R. J. Malik, and J. F. Walker, "New floating-gate AlGaAs/GaAs memory devices with graded-gap electron injector and long retention times," IEEE Electron Device Lett., vol. 9, pp. 377-379, Aug. 1988.
57. K. K. Likharev, "Layered tunnel barriers for nonvolatile memory devices," Appl. Phys. Lett., vol. 73, no. 15, pp. 2137-2139, 1998.
58. S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka, "Reliability issues of flash memory cells," Proc. IEEE, vol. 81, pp. 776-788, May 1993.
59. 2 Films," IEEE Trans. Electron Devices, vol. 45, pp. 1554-1560, July 1998.
60. 2 films," IEEE Trans. Electron Devices, vol. 44, pp. 1002-1008, June 1997.
61. A. Ghetti, E. Sangiorgi, J. Bude, T. W. Sorsch, and G. Weber, "Tunneling into interface states as reliability monitor for ultrathin oxides," IEEE Trans. Electron Devices, vol. 47, pp. 2358-2365, Dec. 2000.
62. C.-M. Yih, Z.-H. Ho, M.-S. Liang, and S. S. Chung, "Characterization of hot-hole injection induced SILC and related disturbs in flash memories," IEEE Trans. Electron Devices, vol. 48, pp. 300-306, Feb. 2001.
63. W. J. Chang, M. P. Houng, and Y. H. Wang, "Simulation of stress-induced leakage current in silicon dioxides: A modified trap-assisted tunneling model considering Gaussian-distributed traps and electron energy loss," J. Appl. Phys., vol. 89, no. 11, pp. 6285-6293, 2001.
64. _, "Electrical properties and modeling of ultrathin impurity-doped silicon dioxides," J. Appl. Phys., vol. 90, no. 10, pp. 5171-5179, 2001.
65. A. Ghetti, A. Hamad, P. J. Silverman, H. Vaidya, and N. Zhao, "Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 1999, pp. 239-242.
66. M. Lenski, T. Endoh, and F. Masuoka, "Analytical modeling of stress-induced leakage currents in 5.1-9.6 nm-thick silicon-dioxide films based on two-step inelastic trap-assisted tunneling," J. Appl. Phys., vol. 88, no. 9, pp. 5238-5245, 2000.
67. L. Larcher, A. Paccagnella, and G. Ghidini, "A model of the stress induced leakage current in gate oxides," IEEE Trans. Electron Devices, vol. 48, pp. 285-288, Feb. 2001.
68. D. Ielmini, A. S. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC based on electron and hole tunneling - Part I: Transient effects," IEEE Trans. Electron Devices, vol. 47, pp. 1258-1265, June 2000.
69. _, "Modeling of SILC based on electron and hole tunneling - Part II: Steady-state," IEEE Trans. Electron Devices, vol. 47, pp. 1266-1272, June 2000.
70. D. Ielmini, A. S. Spinelli, A. L. Lacaita, A. Martinelli, and G. Ghidini, "A recombination- and trap-assisted tunneling model for stress-induced leakage current," Solid-State Electron., vol. 45, no. 8, pp. 1361-1369, 2001.
71. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and G. Ghidini, "Modeling of stress-induced leakage current and impact ionization in MOS devices," Solid-State Electron., vol. 46, no. 3, pp. 417-422, 2002.
72. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, "A new two-trap tunneling model for the anomalous stress-induced leakage current (SILC) in flash memories," Microelectron. Eng., vol. 59, no. 1-4, pp. 189-195, 2001.
73. _, "Modeling of anomalous SILC in flash memories based on tunneling at multiple defects," Solid-State Electron., vol. 46, no. 11, pp. 1749-1756, 2002.
74. R. Moazzami and C. Hu, "Stress-induced current in thin silicon dioxide films," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 1992, pp. 139-142.
75. E. Rosenbaum and L. F. Register, "Mechanism of stress-induced leakage current in MOS capacitors," IEEE Trans. Electron Devices, vol. 44, pp. 317-323, Feb. 1997.
76. S.-I. Takagi, N. Yasuda, and A. Toriumi, "A new I-V model for stress-induced leakage current including inelastic tunneling," IEEE J. Solid-State Circuits, vol. 46, pp. 348-354, Feb. 1999.
77. R. Rofan and C. Hu, "Stress-induced oxide leakage," IEEE Electron Device Lett., vol. 12, pp. 632-634, Nov. 1991.
78. J. Wu, L. F. Register, and E. Rosenbaum, "Trap-assisted tunneling current through ultra-thin oxide," in Proc. Int. Reliability Physics Symp., 1999, pp. 389-395.
79. M. Herrmann and A. Schenk, "Field and high-temperature dependence of the long term charge loss in erasable programmable read only memories: Measurements and modeling," J. Appl. Phys., vol. 77, no. 9, pp. 4522-4540, 1995.
80. A. Palma, A. Godoy, J. A. Jimenez-Tejada, J. E. Carceller, and J. A. Lopez-Villanueva, "Quantum two-dimensional calculation of time constants of random telegraph signals in metal-oxide-semiconductor structures," Phys. Rev. B, vol. 56, no. 15, pp. 9565-9574, 1997.
81. F. Jiménez-Molinos, A. Palma, F. Gámiz, J. Banqueri, and J. A. Lopez-Villanueva, "Physical model for trap-assisted inelastic tunneling in metal-oxide-semiconductor structures," J. Appl. Phys., vol. 90, no. 7, pp. 3396-3404, 2001.
82. F. Jiménez-Molinos, F. Gámiz, A. Palma, P. Cartujo, and J. A. Lopez-Villanueva, "Direct and trap-assisted elastic tunneling through ultrathin gate oxides," J. Appl. Phys., vol. 91, no. 8, pp. 5116-5124, 2002.
83. A. Gehring, F. Jiménez-Molinos, H. Kosina, A. Palma, F. Gámiz, and S. Selberherr, "Modeling of retention time degradation due to inelastic trap-assisted tunneling in EEPROM devices," Microelectron. Reliabil., vol. 43, no. 9-11, pp. 1495-1500, 2003.
84. L. Larcher, "Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model," IEEE Trans. Electron Devices, vol. 50, pp. 1246-1253, May 2003.
85. 2 gate dielectrics for advanced CMOS devices," in Proc. Eur. Solid-State Device Research Conf., J. Franca and P. Freitas, Eds., 2003, pp. 473-476.
86. A. Ghetti, Gate Oxide Reliability: Physical and Computational Models. New York: Springer, 2004, pp. 201-258.
87. M. Alam, B. Weir, J. Bude, P. Silverman, and A. Ghetti, "A computational model for oxide breakdown: Theory and experiments," Microelectron. Eng., vol. 89, no. 1-4, pp. 137-147, 2001.
88. D. J. DiMaria and J. H. Stathis, "Anode hole injection, defect generation, and breakdown in ultrathin silicon dioxide films," J. Appl. Phys., vol. 89, no. 9, pp. 5015-5024, 2001.
89. J. H. Stathis, "Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits," IEEE Trans. Device Mater. Reliabil., vol. 1, pp. 43-59, Mar. 2001.
90. J. Wu, E. Rosenbaum, B. MacDonald, E. Li, J. Tao, B. Tracy, and P. Fang, "Anode hole injection versus hydrogen release: The mechanism for gate oxide breakdown," in Proc. Int. Reliability Physics Symp., 2000, pp. 27-32.
91. 2 dielectrics," J. Appl. Phys., vol. 88, no. 9, pp. 5351-5359, 2000.
92. J. H. Stathis, "Reliability limits for the gate insulator in CMOS technology," IBM J. Res. Dev., vol. 46, no. 2/3, pp. 265-286, 2002.
93. R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, "New insights in the relation between electron trap generation and the statistical properties of oxide breakdown," IEEE Trans. Electron Devices, vol. 45, pp. 904-911, Apr. 1998.
94. J. Suñé, E. Miranda, M. Nafría, and X. Aymerich, "Point contact conduction at the oxide breakdown of MOS devices," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 1998, pp. 191-194.
95. E. Miranda, J. Suñé, R. Rodríguez, M. Nafría, and X. Aymerich, "A function-fit model for the soft breakdown failure mode," IEEE Electron Device Lett., vol. 20, pp. 265-267, June 1999.
96. J. H. Stathis, B. P. Linder, R. Rodríguez, and S. Lombarde, "Reliability of ultra-thin oxides in CMOS circuits," Microelectron. Reliabil., vol. 43, no. 9-11, pp. 1353-1360, 2003.
97. R. Rodríguez, J. H. Stathis, B. P. Linder, R. V. Joshi, and C. T. Chuang, "Influence and model of gate oxide breakdown on CMOS inverters," Microelectron. Reliabil., vol. 43, no. 9-11, pp. 1439-1444, 2003.
98. D. K. Ferry and S. M. Goodnick, Transport in Nanostructures. Cambridge, U.K.: Cambridge University Press, 1997.
99. M. LeRoy, E. Lheurette, O. Vanbesien, and D. Lippens, "Wave-mechanical calculations of leakage current through stacked dielectrics for nanotransistor metal-oxide-semiconductor design," J. Appl. Phys., vol. 93, no. 5, pp. 2966-2971, 2003.
100. C. M. Osburn, I. Kim, S. K. Han, I. De, K. F. Yee, S. Gannavaram, S. J. Lee, C.-H. Lee, Z. J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T. P. Ma, and M. C. Öztürk, "Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?," IBM J. Res. Dev., vol. 46, no. 2/3, pp. 299-315, 2002.
101. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, 2001.
102. J. Robertson, "Band offsets of wide-bandgap oxides and implications for future electronic devices," J. Vac. Sci. Technol., vol. 18, no. 3, pp. 1785-1791, 2000.
103. H.-S. P. Wong, "Beyond the conventional transistor," IBM J. Res. Dev., vol. 46, no. 2/3, pp. 133-168, 2002.
104. J. Zhang, J. S. Yuan, Y. Ma, and A. S. Dates, "Design optimization of stacked layer dielectrics for minimum gate leakage currents," Solid-State Electron., vol. 44, no. 12, pp. 2165-2170, 2000.
105. 2," Solid-State Electron., vol. 20, no. 1, pp. 11-18, 1977.
106. 2/Si structures," Solid-State Electron., vol. 38, no. 8, pp. 1465-1471, 1995.
107. F. Rana, S. Tiwari, and D. A. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, no. 8, pp. 1104-1106, 1996.
108. 2-Si structures with ultra-thin oxide layer," Microelectron. Eng., vol. 59, no. 1-4, pp. 127-136, 2001.
109. J. Cai and C.-T. Sah, "Gate tunneling currents in ultrathin oxide metal-oxide-silicon transistors." J. Appl. Phys., vol. 89, no. 4, pp. 2272-2285, 2001.