A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization

Microelectronics Reliability

Volumn 43, Issue 1, 2003, Pages 17-41

  Ruprecht, Michael ^a   Benstetter, Guenther ^b   Hunt, Doug ^c  

^a INFINEON TECHNOLOGIES   (United States)

^b DEGGENDORF INSTITUTE OF TECHNOLOGY   (Germany)

^c IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; FAILURE ANALYSIS; ION BEAMS; MICROSCOPES; ULSI CIRCUITS;

DEFECT ISOLATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0037229036     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(02)00295-0     Document Type: Review

References (81)

1. Benstetter G, Ruprecht M, Hunt D. A review of USLI failure analysis techniques for trench technology DRAMs, Part I: Defect localization and verification. Microelectron Reliab 2002;42:307-16.
2. Griep S., Khare J., Lemme R., Papenberg U., Schmitt-Landsiedel D., Maly W.et al. Application of defect simulation as a tool for more efficient failure analysis. Qual. Reliab. Eng. Int. 10:1994;297-302.
3. Beck F. Praeparationstechniken fuer die Fehleranalyse an integrierten Halbleiterschaltungen. 1988;VCH Verlagsgesellschaft, Weinheim. [in German].
4. Campbell St.A. The science and engineering of microelectronic fabrication. 1996;Oxford University Press, New York, Oxford.
5. Spinella C. Chemical and electrochemical staining for two-dimensional dopant concentration profiling on USLI silicon devices. In: Defects and Diffusion in Silicon Processing, Material Research Society Symposium Proceedings, Warrendale, PA, vol. 469, April 1997. p. 323-8.
6. Oh CK, Wu ZM, Redkar S. A new deprocessing technique by selective wet-etch of passivation and inter metal dielectric layers for submicron devices. In: ISTFA 2001, 27th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 2001. p. 319-22.
7. Corum D, Chowdhury R. Practical applications of backside silicon etching. In: ISTFA 95, 21st International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 1995. p. 263-8.
8. Bellon L., Sardin P., Bicais Lepinay N., Decroix L., Weiland R. Failure analysis preparation: a system assessment. Semicond. Int. 22(8):1999;171-172. 176, 180.
9. Harriot L.R. Focused ion beam induced gas etching. Jpn. J. Appl. Phys. 1. 33:1994;7094-7098.
10. Li SX, Gray A. How to decorate FIB cross sections using plasma etch for SEM observation. In: ISTFA 95, 21st International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 1995. p. 347-51.
11. Perez G., Coutade F., Benteo B., Lin-Kwan J. Layers decoration on FIB cross-sections. Microelectron. Reliab. 37:1997;1611-1614.
12. Huffman KV, Hoener CF, Shaver B. FIB sample preparation to reduce charging for Auger analysis (IC failure analysis). In: ISTFA 94, 20th International Symposium for Testing and Failure Analysis, Los Angeles, November 1994. p. 365-75.
13. Benstetter G, Bomberger G, Coutu P, Danyew R, Douse R. Failure analysis of DRAM storage node trench capacitors for 0.35-micron and follow on technologies using the focused ion beam for electrical and physical analysis. In: ISTFA 1996, Proceedings of the 22nd International Symposium for Testing and Failure Analysis, Los Angeles, CA, November 1996. p. 401-7.
14. Birnie A., Beaumont A., Dodd C., McNeil G. Advanced FIB applications for product analysis. SPIE. Vol. 2635:1995;178-186.
15. Verkleij D. The use of the focused ion beam in failure analysis. Microelectron. Reliab. 38:1998;869-876.
16. Ruprecht MW, Wen Sh, Vollertsen RP. Sample preparation for vertical transistors in DRAM. In: ISTFA 2002, 28th International Symposium for Testing and Failure Analysis, Phoenix, AZ, November 2002. p. 307-12.
17. Zimmermann G, Johnston M, Christ R. A focused ion beam technique to electrically contact the deep trench capacitor of a single active memory cell in the sub 0.25 μ m technology regime. In: ISTFA 2001, 27th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 2001. p. 225-30.
18. Rai R, Subramanian S, Rose St, Conner J, Schani R, Moss J. Specific area planar and cross-sectional lift-out techniques: procedures and novel applications. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 415-24.
19. King R.G., Delaney P.M. Confocal microscopy. Mater. Forum (Australia). vol. 18:1994;21-29.
20. Scheele J. Confocal scanning tackles submicron inspection. Eur. Semicond. 16(5):1994;19.
21. Hecht E. Optics. 2002;Addison Wesley, Boston.
22. Krueger D., Rosenkranz R., Tippelt B., Kuhnert M., Griessbach K., Lamprecht A., et al. Failure mode analysis of a 0.25. μ m CMOS technology by scanning electron and ion beam Solid State Phenom. 63-64:1998;433-442.
23. Tamatsuka M., Miki K. Gate oxide defect analysis using scanning electron microscopy (SEM)/metal oxide semiconductor (MOS)/electron beam induced current (EBIC) with subnano ampere current breakdown. Solid State Phenom. 63-64:1998;395-406.
24. Muehle U., Wiesner A., Schray S. Detailed investigation of SEM-results by TEM at one sample using FIB-technique. Microelectron. Reliab. 38:1998;895-899.
25. Yang X, Song X. The application of FIB voltage contrast technique combining with TEM on subtle defect analysis: via delamination after TC. In: ISTFA 97, 23st International Symposium for Testing and Failure Analysis, Santa Clara, CA, October 1997. p. 115-9.
26. Ohring M. The materials science of thin films. 1992;Academic Press, San Diego.
27. Ohring M. Reliability and failure of electronic materials and devices. 1998;Academic Press, San Diego.
28. Rose J.H., Miner B., Pelillo A. Transmission electron microscopy: a review and a comparison with high resolution scanning electron microscopy. Lee T.W. Microelectronic failure analysis, desk reference. 1995;ASM International.
29. Marcus R.B., Sheng T.T. Transmission electron microscopy of silicon VLSI circuits and structures. 1983;John Wiley and Sons, New York.
30. Runyan W.R., Shaffner T.J. Semiconductor measurements and instrumentation. 1998;McGraw-Hill, New York.
31. Zhang H. What limits the application of TEM in the semiconductor industry. Thin Solid Films. 320:1998;77-85.
32. Zhang H. Application of TEM on sub half micron semiconductor devices. In: Electron Microscopy of Semiconducting Materials and ULSI Devices, Symposium, San Francisco, CA, April 1998. p. 45-56.
33. Mendez H., Morris S., Tatti S., Dickson N., Pyle R.E. Imaging gate oxide ruptures. SPIE. vol. 1802:1992;126-133.
34. Leslie AJ, Pey KL, Sim KS, Beh MTF, Goh GP. TEM sample preparation using FIB: practical problems and artefacts. In: ISTFA 95, 21st International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 1995. p. 353-62.
35. Mardinly J, Susnitzky DW. Transmission electron microscopy of semiconductor based products. In: Electron Microscopy of Semiconducting Materials and ULSI Devices, Symposium, San Francisco, CA, April 1998. p. 3-12.
36. Wang N, Fang R. Combining FIB sequential cross sectioning with TEM for small defect analysis in SRAM array. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 309-14.
37. Tsung L, Anciso A, Turner R, Dixon Th, Holoway N. Mass production cross-section TEM sample preparation of focus ion beam masking and reactive ion etching. In: ISTFA 2001, 27th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 2001. p. 299-302.
38. Cerva H, Hammerl E, Lemme R, Schwalke U, Wangemann K, Zoth G. Characterization of process induced defects in silicon technology. In: 3rd International Symposium on Defects in Silicon, Seattle, WA, May 1999. p. 55-67.
39. Giewont K.J., Hunt D.B., Hummler K.M. Probeless voltage contrast using focused ion beam for opens and short defect isolation of ultralarge scale integration technologies. J. Vac. Sci. Technol. B. 15:1997;916-920.
40. Campbell AN, Soden JM, Rife, Lee RG. Electrical biasing and voltage contrast imaging in a focused ion beam system. In: Proceedings of the International Symposium for Testing and Failure Analysis, November 1995. p. 33-50.
41. Danyew R, Douse R, Coutu P, Clark W, Berman H. Analytical techniques and procedures to successfully locate and characterize memory storage node trench defects. In: Proceedings of the International Symposium for Testing and Failure Analysis, 1990. p. 323-29.
42. Benstetter G, Vollertsen R-P, Bomberger G, Coutu P, Danyew R, Douse R. Reliability and failure analysis of 64 Mbit and 256 Mbit DRAM trench capacitors. In: Proceedings of the GMM-Conference, Munich, 1997. p. 251-8.
43. Howland R., Benatar L. A practical guide to scanning probe microscopy. 1996;Park Scientific Instruments, Sunnyvale, CA.
44. Ebel J, Bozada C, Schlesinger T, Cerny C, DeSalvo G, Dettmet R, et al. Cross-sectional atomic force microscopy of focused ion beam milled devices. In: IEEE International Reliability Physics Symposium, Reno, NV, April 1998. p. 157-62.
45. Neubauer G., Lawrence M., Dass A., Johnson T.J. Imaging VLSI cross sections by atomic force microscopy. Mater. Res. Soc. Symp. Proc. 265:1992;283-288.
46. Born A., Olbrich A., Maywald M., Wiesendanger R. Analysis of electrical breakdown failures by means of SFM based methods. Appl. Phys. A: Mater. Sci. Process. 66:1998;S1063-S1065.
47. Fabricius A, Breternitz V, Knedlik C, Henning A, Liebscher E, Vogel S. Investigation of electromigration failure by electrical measurements and scanning probe microscopy with additional simulation. In: Materials Reliability in Microelectronics VIII, Symposium, San Francisco, April 1998. p. 27-32.
48. Pey KL, Strausser YE, Erickson AN, Leslie AJ, Beh MTHF, Sheng TT. Scanning capacitance microscopy analysis of DRAM trench capacitors. In: IEEE International Workshop on Memory Technology, Design and Testing, Singapore, August 1996. p. 79-85.
49. Erickson AN, Adderton DM, Strausser YE, Tench RJ. Scanning capacitor microscopy for carrier profiling in semiconductors. di Digital instruments, August 1999. Available: www.DI.com/appnotes/SCM/SCMMain.html.
50. Neubauer G., Erickson A., Williams C.C., Kopanki J.J., Rodgers M., Adderton D. Two-dimensional scanning capacitance microscopy measurements of cross-sectioned very large scale integration test structures. J. Vac. Sci. Technol. B. 14:1996;426-432.
51. Ebersberger B, Boit B, Benzinger H, Guenther E. Thickness mapping of thin dielectrics with emission microscopy and conductive atomic force microscopy for assessment of dielectrics reliability. In: Annual Proceedings Reliability Physics IEEE, Piscataway, USA, May 1996. p. 126-30.
52. Born A, Wiesendanger R. Guidelines for two-dimensional dopant profiling using SCM. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 521-8.
53. 2 with conducting AFM. In: Proceedings of IEEE International Reliability Physics Symposium (36th IRPS), Reno, NV, 1998. p. 163.
54. Olbrich A., Ebersberger B., Boit C. Thickness mapping and microscopic electrical characterization of thin dielectrics with emission microscopy and conducting AFM. Future Fab Int. (5):1998;361.
55. Olbrich A, Ebersberger B, Boit C. Local electrical thickness mapping of thin oxides with conducting atomic force microscopy. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 511-20.
56. 2 films with conducting atomic force microscopy. In: IEEE 01CH37 167, 39th Annual International Reliability Symposium, Orlando, 2001.
57. Ebersberger B, Boit C, Benzinger H, Günther E. In: Proceedings of IEEE International Reliability Physics Symposium (34th IRPS), Austin, TX, 1996. p. 126.
58. Olbrich A., Ebersberger B., Boit C., Niedermann Ph., Hänni W., Vancea J. et al. High aspect ratio diamond tips formed by FIB for conducting AFM. J. Vac. Sci. Technol. B. 17(4):1999;1570.
59. Landau SA, Kolbesen BO, Tillmann R, Buchaus R, Olbrich A, Fritsch E, et al. Characterisation of novel high-epsilon dielectric and ferroelectric films by scanning probe microscopy (SPM) techniques. In: Semiconductor Silicon-98, Electrochemical Society Proceedings, Vol. 98-1, 1998. p. 789-97.
60. Olbrich A, Ebersberger B, Boit C, Vancea J, Hoffmann H. A new AFM-based tool for testing dielectric quality and reliability on nanometer scale. In: Proceedings of the 10th European Symposium on Reliability of Electronic Devices, Failure Physics and Analysis, Bordeaux, France, 1999.
61. Yuwono B, Schlösser T, Gschwandtner A, Inertsberger G, Graßl A, Olbrich A, et al. Reliability of ultrathin oxide an nitride films in the 1 nm to 2 nm range. In: Proceedings of Insulating Films on Semiconductors (INFOS'99), Erlangen, Germany, 1999.
62. 2 breakdown spots using C-AFM. J. Non-Cryst. Solids. 280:2001;138-142.
63. Landau S.A., Junghans N., Weiß P.A., Kolbesen B.O., Olbrich A., Schindler G.et al. Scanning probe microscopy - a tool for the investigation of high-k materials. Appl. Surf. Sci. 157:2000;387-392.
64. 2 on Si. In: 11th Workshop on Dielectrics in Microelectronics (2000), Munich, Germany. Microelectron Reliab 2001;41(7):1077-9.
65. 2 films observed with conductive atomic force microscope. Microelectron. Reliab. 41:2001;1041-1044.
66. 2 layers detected by C-AFM. Nanotechnology. 12:2001;164-167.
67. 2 films. In: IRW 2002, Integrated Reliability Workshop, Stanford Sierra Camp, Fallen Leaf Lake, CA, October 2002. Accepted.
68. Frammelsberger W, Benstetter G, Stamp RJ, Kiely J. Combined AFM methods to improve reliability investigations of thin oxides. In: IRW 2002, Integrated Reliability Workshop, Stanford Sierra Camp, Fallen Leaf Lake, CA, October 2002. Accepted.
69. Perdu P, Desplats R, Beaudoin F. A review of sample backside preparation techniques for VLSI. In: 11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Dresden, October 2000. p. 431-6.
70. Desplates R, Beaudoin F, Perdu Ph. CNC milling and polishing techniques for backside sample preparation. In: International Symposium for Testing and Failure Analysis (ISTFA), Santa Clara, CA, November 2001. p. 179-87.
71. Ruprecht MW, Pollock TP, Kontra RS, Berry WS. Physical failure analysis on vertical dielectric films. In: International Symposium for Testing and Failure Analysis (ISTFA), Santa Clara, CA, November 2001. p. 331-41.
72. Beaudoin F, Saviot F, Lewis D, Perdu P, Salin F. New non-destructive laser ablation based backside sample preparation method. In: 11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Dresden, October 2000. p. 425-9.
73. Bernhard-Hoefer K., Barton D.L., Cole E.I. FLIP-chip and "backside" techniques. Microelectronic failure analysis, desk reference 4th edition. 1999;ASM International, Materials Park, OH. p. 487-504.
74. Davis D, Diaz de Leon O, Hughes L, Pabbisetty SV, Parker R, Scott P, et al. Failure analysis of advanced microprocessors through backside approaches. In: ISTFA 98, 24th International Symposium for Testing and Failure Analysis, Dallas, TX, November 1998. p. 473-82.
75. Trigg A, Yong LP. Sample preparation for backside failure analysis using infrared photoemission microscopy. In: ISTFA 99, 25th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 1999. p. 117-24.
76. Liebert S. Failure analysis from the back side of a die. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 177-85.
77. Nishida A, Sekiguchi T, Yamanaka T, Yamada R, Nakamura K, Tomimatsu S, et al. Visualization of local gate depletion in PMOSFETs using unique backside etching and selective etching techniques. In: ISTFA 99, 25th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 1999. p. 413-8.
78. Lee J, Huang KH, Lue J-L. A novel method to analyze the deep trench capacitors in DRAM. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 241-4.
79. Zachariasse F. CMOS front-end investigation over large areas by deprocessing from the back side. In: ISTFA 2001, 27th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 2001. p. 237-41.
80. Morris M, Mohr J, Ortiz E, Englebretson S. The use of TMAH to etch silicon and expose metal bridging failures. In: ISTFA 2000, 26th International Symposium for Testing and Failure Analysis, Seattle, WA, November 2000. p. 231-4.
81. Dübotzky A, Krüger B. Evaluation of alternative preparation methods for failure analysis at modern chip- and package technologies. In: ISTFA 2001, 27th International Symposium for Testing and Failure Analysis, Santa Clara, CA, November 2001. p. 83-6.