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0036045245
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A Highly Manufacturable 110nm DRAM Technology with 8F 2 Vertical Transistor Cell for 1Gb and Beyond
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Honolulu, Hawaii, June
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H.Akatsu, R.Weis, K.Cheng, M.Seitz, M-S.Kim, R.Ramachandran, T.Dyer, B.Kim, D-K.Kim, R.Malik, J.Strane, T.Goebel, O-J.Kwon, CY.Sung, P.Parkinson, K.Wilson, I.McStay, M.Chudzik, D.Dobuzinsky, M.Jacunski, C.Ransom, K.Settlemyer, L.Economikos, A.Simpson, A.Knorr, M.Naeem, G.Stojakovic, W.Robl, O.Gluschenkov, B.Liegl, C-H.Wu, Q.Wu, W-K. Li, CJ.Choi, N.Arnold, T.Joseph, K.Varn, M.Weybright, K.McStay, W-T.Kang, Y.Li, S.Bukofsky, R.Jammy, R.Schutz, A.Gutmann, W.Bergner, R.Divakaruni, D.Back, E.Crabbé, W.Mueller, and G.Bronner: A Highly Manufacturable 110nm DRAM Technology with 8F 2 Vertical Transistor Cell for 1Gb and Beyond, IEEE VLSI Symposia on technology, Honolulu, Hawaii, June 2002
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IEEE VLSI Symposia on Technology
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Akatsu, H.1
Weis, R.2
Cheng, K.3
Seitz, M.4
Kim, M.-S.5
Ramachandran, R.6
Dyer, T.7
Kim, B.8
Kim, D.-K.9
Malik, R.10
Strane, J.11
Goebel, T.12
Kwon, O.-J.13
Sung, C.Y.14
Parkinson, P.15
Wilson, K.16
McStay, I.17
Chudzik, M.18
Dobuzinsky, D.19
Jacunski, M.20
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Settlemyer, K.22
Economikos, L.23
Simpson, A.24
Knorr, A.25
Naeem, M.26
Stojakovic, G.27
Robl, W.28
Gluschenkov, O.29
Liegl, B.30
Wu, C.-H.31
Wu, Q.32
Li, W.-K.33
Choi, C.J.34
Arnold, N.35
Joseph, T.36
Varn, K.37
Weybright, M.38
McStay, K.39
Kang, W.-T.40
Li, Y.41
Bukofsky, S.42
Jammy, R.43
Schutz, R.44
Gutmann, A.45
Bergner, W.46
Divakaruni, R.47
Back, D.48
Crabbé, E.49
Mueller, W.50
Bronner, G.51
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0242695792
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A 110nm 512Mb DDR DRAM with Vertical Transistor Trench Cell
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Honolulu, Hawaii, June
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S. Wuensche, M. Jacunski, H. Streif, A. Sturm, J. Morrish, M. Roberge, M. Clark, T. Nostrand, E. Stahl, S. Lewis, J. Heath, M. Wood, T. Vogelsang, E. Thoma, J. Gabric, M. Kleiner, M. Killian, P. Poechmueller, W. Mueller and G. Bronner: A 110nm 512Mb DDR DRAM with Vertical Transistor Trench Cell, IEEE VLSI Symposia on circuits, Honolulu, Hawaii, June 2002
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IEEE VLSI Symposia on Circuits
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Wuensche, S.1
Jacunski, M.2
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0034454628
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An Orthogonal 6F2 Trench Sidewall Vertical Device Cell for 4Gb/16Gb DRAM
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San Francisco, CA
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Radens C.J., Kudelka S., Nesbit L., Malik R., Dyer T., Dubuc C., Joseph T., Seitz M., Clevenger L., Arnold N., Mandelman J., Divakaruni R., Casarotto D., Lea D., Jaiprakash V.C., Sim J., Faltermaier J., Low K., Strane K., Halle J., Ye Q., Bukofsky S., Gruening U., Schloesser T. and Bronner G.: An Orthogonal 6F2 Trench Sidewall Vertical Device Cell for 4Gb/16Gb DRAM, International Electron Devices Meeting IEDM, San Francisco, CA, 2000, pp.349-52
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The Evolution of IBM CMOS DRAM Technology
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January/March
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Adler E, DeBrosse JK, Geissler SF, Holmes SJ, Jaffe MD, Johnson JB, Koburger CW, Lasky JB, Lloyed B, Miles GL, Nakos JS, Noble WP Jr., Voldman SH, Armacost M, Ferguson R.: The Evolution of IBM CMOS DRAM Technology, IBM J. Res. Develop. Vol 39, No 1/2, January/March 1995, pp. 167-187.
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1542330624
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Physical Failure Analysis on Vertical Dielectric Films
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Santa Clara, CA
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Ruprecht M.W., Pollock T.P., Kontra R.S. and Berry W.S.: Physical Failure Analysis on Vertical Dielectric Films, International Symposium for Testing and Failure Analysis (ISTFA) November 2001, Santa Clara, CA, 331-41.
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Ruprecht, M.W.1
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New Global Insight in Ultra-Thin Oxide Reliability Using Accurate Experimental Methodology and Comprehensive Database
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