Physical Failure Analysis on Vertical Dielectric Films

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2001, Pages 331-341

  Ruprecht, Michael W ^a   Pollock, Timothy P ^b   Kontra, Richard S ^b   Berry, Wayne S ^b  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FOCUSED ION BEAMS (FIB); ION BEAM MILLING; MECHANICAL POLISHING;

CAPACITORS; DYNAMIC RANDOM ACCESS STORAGE; ETCHING; FAILURE ANALYSIS; ION BEAMS; MILLING (MACHINING); POLISHING; SCANNING ELECTRON MICROSCOPY; TRANSMISSION ELECTRON MICROSCOPY;

DIELECTRIC FILMS;

EID: 1542330624     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Kasai N.: Trend in DRAM structures and processes to giga-bit generations, NEC Res. Dev., Vol.40, No.3, July 1999, 267-71
2. 2 256Mb trench DRAM cell with self-aligned buriEd STrap (BEST), International Electron Devices Meeting IEDM, Washington DC, 1993, pp. 627-30
3. Bronner G., Aochi H., Gall M., Gambino J., Gernhardt S., Hammer E., Ho H., Iba I., Ishiuchi H., Jaso M., Kleinhenz R., Mii T., Narita M., Nesbit L., Neumueller W., et.al.: Fully planarized 0.25um CMOS technology for 256Mbit DRAM and beyond, Proc. of the 1995 Symposium on VSLI Technology, Digest of technical papers, IEEE, Piscataway, NJ, 1995, pp. 15-6
4. Radens C.J., Kudelka S., Nesbit L., Malik R., Dyer T., Dubuc C., Joseph T., Seitz M., Clevenger L., Arnold N., Mandelman J., Divakaruni R., Casarotto D., Lea D., Jaiprakash V.C., Sim J., Faltermaier J., Low K., Strane K., Halle J., Ye Q., Bukofsky S., Gruening U., Schloesser T. and Bronner G.: An orthogonal 6F2 trenh sidewall vertival device cell for 4Gb/16Gb DRAM, International Electron Devices Meeting IEDM, San Francisco, CA, 2000, pp.349-52
5. Adler E, DeBrosse JK, Geissler SF, Holmes SJ, Jaffe MD, Johnson JB, Koburger CW, Lasky JB, Lloyed B, Miles GL, Nakos JS, Noble WP Jr., Voldman SH, Armacost M, Ferguson R.: The Evolution of IBM CMOS DRAM technology, IBM J. Res. Develop. Vol 39, No 1/2, January/March 1995, pp. 167-187.
6. Muller K.P., Flietner B., Hwang C.L., Kleinhenz R.L., Nakao T., Ranade R., Tsunashima Y., Mii T.: Trench Storage Node Technology for Gigabit DRAM Generations, IEDM, 507-510 (1996)
7. Aoki M, Ozaki T., Yamada T., Kawaguchiya H., Ishibashi Y. and Hamamoto T.: Fully self-aligned 6F2 cell technology for low cost 1Gb DRAM, Proc. of the 1996 Symposium on VSLI Technology, Digest of technical papers, IEEE, Piscataway, NJ, 1996, pp. 22-3
8. Koelzer J.: Emission microscopy: principles and applications, Defect Recognition and Image Processing in Semiconductor and Device Conference, Santander, Spain, September 1993, pp. 351-60
9. nd International Symposium for Testing and Failure Analysis, Los Angeles CA, November 1996, pp 401-7
10. th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Dresden, October 2000, pp. 1431-6
11. th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Dresden, October 2000, pp. 1425-9
12. th Edition, ASM International, Materials Park, Ohio, 1999, pp 487-504
13. th International Symposium for Testing and Failure Analysis, Dallas, TX, November 1998, pp. 473-82
14. th International Symposium for Testing and Failure Analysis, Santa Clara, November 1999, pp.117-24
15. th International Symposium for Testing and Failure Analysis, Seattle, Washington, November 2000, pp. 177-85
16. th International Symposium for Testing and Failure Analysis, Santa Clara, November 1999, pp.413-18
17. th International Symposium for Testing and Failure Analysis, Seattle, Washington, November 2000, pp. 241-4
18. th Edition, ASM International, Materials Park, Ohio, 1999, pp 315-26