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Volumn , Issue , 1999, Pages 413-418

Visualization of Local Gate Depletion in PMOSFETs Using Unique Backside Etching and Selective Etching Technique

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION; DOPING (ADDITIVES); ELECTROCHEMICAL ELECTRODES; ETCHING; FAILURE ANALYSIS; GATES (TRANSISTOR); LSI CIRCUITS; SCANNING ELECTRON MICROSCOPY; SECONDARY ION MASS SPECTROMETRY; SILICON WAFERS; TRANSCONDUCTANCE; TRANSMISSION ELECTRON MICROSCOPY;

EID: 0012408924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (10)
  • 4
    • 0021201723 scopus 로고
    • (100) Silicon Etch-Rate Dependence on Boron Concentration in Ethylenediamine-Pyrocatechle-Water Solution
    • N. F. Raley, Y. Sugiyama and T. Van Duzer, "(100) Silicon Etch-Rate Dependence on Boron Concentration in Ethylenediamine-Pyrocatechle-Water Solution", J. Electrochem. Soc., p. 161, 131(1984)
    • (1984) J. Electrochem. Soc. , pp. 161
    • Raley, N.F.1    Sugiyama, Y.2    Van Duzer, T.3
  • 5
    • 0016496213 scopus 로고
    • Optimization of the Hydrazine-Water Solution for An Isotropic Etching of Silicon in Integrated Circuit Technology
    • M. J. Declercq, L. Gerzberg and J. D. Meindl, "Optimization of the Hydrazine-Water Solution for An Isotropic Etching of Silicon in Integrated Circuit Technology", J. Electorchem. Soc., p. 545, 122(1975)
    • (1975) J. Electorchem. Soc. , pp. 545
    • Declercq, M.J.1    Gerzberg, L.2    Meindl, J.D.3
  • 6
    • 0029521766 scopus 로고
    • A Scaled 1.8V, 0.18 μm Gate Length CMOS Technology: Device Design and Reliability Considerations
    • M. Rodder, S. Aur and I. -C. Chen, "A Scaled 1.8V, 0.18 μm Gate Length CMOS Technology: Device Design and Reliability Considerations", IEDM Tech. Dig. p. 415(1995)
    • (1995) IEDM Tech. Dig. , pp. 415
    • Rodder, M.1    Aur, S.2    Chen, I.-C.3
  • 8
    • 84886448106 scopus 로고    scopus 로고
    • Effects of Gate Depletion and Boron Penetration on Matching of Deep Submicron CMOS Transistors
    • H. P. Tuinhout, A. H. Montree, J. Schmitz and P. A. Stolk, "Effects of Gate Depletion and Boron Penetration on Matching of Deep Submicron CMOS Transistors", IEDM Tech. Dig. p. 631-634(1997)
    • (1997) IEDM Tech. Dig. , pp. 631-634
    • Tuinhout, H.P.1    Montree, A.H.2    Schmitz, J.3    Stolk, P.A.4
  • 10
    • 0025530908 scopus 로고
    • Effects of Depleted Poly-Si Gate on MOSFET Performance
    • M. Iwase and S. Takagi, "Effects of Depleted Poly-Si Gate on MOSFET Performance", Extended abstracts of SSDM, p. 271 (1990)
    • (1990) Extended Abstracts of SSDM , pp. 271
    • Iwase, M.1    Takagi, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.