Failure analysis preparation: A system assessment

Semiconductor International

Volumn 22, Issue 8, 1999, Pages

  Bellon, Laurent ^a   Sardin, Philippe ^a   Bicais Lepinay, Nadine ^a   Decroix, Luc ^a   Weiland, Rainer ^a  

^a BPS Nextral   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; ELECTRONICS PACKAGING; ETCHING; FAILURE ANALYSIS; MASKS; REVERSE ENGINEERING; SEMICONDUCTOR DEVICE TESTING; SILICON WAFERS; STRESS ANALYSIS;

DESIGN OF EXPERIMENTS (DOE);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0032682198     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)