CNC Milling and Polishing Techniques for Backside Sample Preparation

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2001, Pages 179-187

  Desplats, Romain ^a   Beaudoin, Felix ^a   Perdu, Philippe ^a  

^a CNES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC FORCE MICROSCOPY; MICROPROCESSOR CHIPS; MILLING (MACHINING); NETWORKS (CIRCUITS); PLASTIC MOLDS; POLISHING; SILICON;

CIRCUIT FAILURES;

FAILURE ANALYSIS;

EID: 1542300712     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Barton D.L., Bernhard-Höfer K. and Cole Jr. E.I. Microelec. Reliab. (1999) 721-730.
2. Philippe Perdu, Romain Desplats, Felix Beaudoin, "Comparative Study of Sample Preparation Techniques for Backside Analysis", ISTFA, 12-16 November 2000 Seattle (USA).
3. T Lundquist, E Delenia, J Harroun, E LeRoy and C-C Tsao, "Ultra-thinning of C4 integrated circuits for backside analysis during first silicon debug", ESREF, 2-5 October, 2001 Bordeaux, France.