Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability

IEEE Transactions on Device and Materials Reliability

Volumn 10, Issue 3, 2010, Pages 390-395

  Saurabh, Sneh ^a   Kumar, M Jagadesh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

CMOS technology; process induced variations; strain; tunnel field effect transistor (TFET)

Indexed keywords

CHANNEL LENGTH; CMOS TECHNOLOGY; DEVICE SIMULATIONS; DOUBLE-GATE; ELECTRICAL CHARACTERISTIC; ESTIMATION AND COMPENSATION; GATE OXIDE; IMPROVED RELIABILITY; LOW-LEAKAGE CURRENT; NANO SCALE; ON-CURRENTS; POSSIBLE SOLUTIONS; PROCESS VARIATION; PROCESS-INDUCED VARIATION; SHORT-CHANNEL EFFECT; SILICON THIN FILM; SUBTHRESHOLD SWING;

CMOS INTEGRATED CIRCUITS; FILM THICKNESS; GATES (TRANSISTOR); LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS;

FIELD EFFECT TRANSISTORS;

EID: 77957000706     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2010.2054095     Document Type: Article

References (55)

1. J. Knoch and J. Appenzeller, "A novel concept for field-effect transistors-The tunneling carbon nanotube FET," in Proc. 63rd DRC, Jun. 2005, pp. 153-156. (Pubitemid 44802654)
2. S. O. Koswatta, D. E. Nikonov, and M. S. Lundstrom, "Computational study of carbon nanotube p-i-n tunnel FETs," in IEDM Tech. Dig., 2005, pp. 518-521.
3. J. Appenzeller, Y. M. Lin, J. Konch, Z. Chen, and P. Avouris, "Comparing carbon nanotube transistors-The ideal choice: A novel tunneling device design," IEEE Trans. Electron Devices, vol.52, no.12, pp. 2568-2576, Dec. 2005. (Pubitemid 41824835)
4. S. Poli, S. Reggiani, A. Gnudi, E. Gnani, and G. Baccarani, "Computational study of the ultimate scaling limits of CNT tunneling devices," IEEE Trans. Electron Devices, vol.55, no.1, pp. 313-321, Jan. 2008.
5. J. Konch, S. Mantl, and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices," Solid State Electron., vol.51, no.4, pp. 572-578, Apr. 2007. (Pubitemid 46550579)
6. S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, "Performance comparison between p-i-n tunneling transistors and conventional MOSFETs," IEEE Trans. Electron Devices, vol.56, no.3, pp. 456-465, Mar. 2009.
7. A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. D. Gendt, M. M. Heyns, and G. Groesenrken, "Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates," IEEE Electron Device Lett., vol.29, no.12, pp. 1398-1401, Dec. 2008.
8. T. Nirschl, P. F. Wang, C. Weber, J. Sedlmeir, R. Heinrich, R. Kakoschke, K. Schrufer, J. Holz, C. Pacha, T. Schulz, M. Ostermayr, A. Olbrich, G. Georgakos, E. Ruderer, W. Hansch, and D. Schmitt-Landsiedel, "The tunneling field effect transistor (TFET) as an add-on for ultra-lowvoltage analog and digital processes," in IEDM Tech. Dig., Dec. 2004, pp. 195-198. (Pubitemid 40928261)
9. A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, "Modeling the single-gate, double-gate, and gate-allaround tunnel field-effect transistor," J. Appl. Phys., vol.107, no.2, pp. 024518-1-024518-8, Jan. 15, 2010.
10. C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, "Lateral interband tunneling transistor in silicon-on-insulator," Appl. Phys. Lett., vol.84, no.10, pp. 1780-1782, Mar. 2004.
11. R. Jhaveri, Y. L. Chao, and J. C. S.Woo, "Novel MOSFET devices for RF circuits applications," in Proc. ICSICT, Oct. 2006, pp. 43-46.
12. V. V. Nagavarapu, R. R. Jhaveri, and J. C. S. Woo, "The tunnel source (PNPN) n-MOSFET: A novel high performance transistor," IEEE Trans. Electron Devices, vol.55, no.4, pp. 1013-1019, Apr. 2008.
13. N. Venkatagirish, R. Jhaveri, A. Tura, and J. C. S. Woo, "Novel asymmetric MOSFET structures for low power applications," in Proc. EDSSC, Dec. 2008, pp. 1-6.
14. V. Dobrovolsky, V. Rossokhaty, and S. Cristoloveanu, "Contunt: Thin SOI control tunneling transistor," Solid State Electron., vol.50, no.5, pp. 754-757, May 2006. (Pubitemid 43849866)
15. K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high gate dielectric," IEEE Trans. Electron Devices, vol.54, no.7, pp. 1725-1733, Jul. 2007. (Pubitemid 47061885)
16. E. H. Toh, G. H.Wang, L. Chan, D. Sylvester, C. H. Heng, G. S. Samudra, and Y. C. Yeo, "Device design and scalability of a double-gate tunneling field-effect transistor with silicon-germanium source," Jpn. J. Appl. Phys., vol.47, no.4, pp. 2593-2597, Apr. 2008.
17. E. H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y. C. Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction," Appl. Phys. Lett., vol.91, no.24, p. 243505, Dec. 2007. (Pubitemid 350262045)
18. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Tunnel field-effect transistor without gate-drain overlap," Appl. Phys. Lett., vol.91, no.5, p. 053102, Jul. 2007. (Pubitemid 47210836)
19. S. Saurabh and M. J. Kumar, "Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis," Jpn. J. Appl. Phys., vol.48, pt. 1, no.6, p. 064503, Jun. 2009.
20. T. Uemura and T. Baba, "A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistor," IEEE Trans. Electron Devices, vol.49, no.8, pp. 1336-1340, Aug. 2002. (Pubitemid 32877525)
21. M. Fulde, A. Heigl, G. Wachutka, G. Knoblinger, and D. Schmitt-Landsiedel, "Complementary multi-gate tunnelling FETs: Fabrication, optimisation and application aspects," Int. J. Nanotechnol., vol. 6, no. 7/8, pp. 628-639, 2009.
22. F. Mayer, C. L. Royer, J. F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, "Impact of SOI, Si1xGexOI and GeOI substrates on CMOS compatible tunnel FET performance," in IEDM Tech. Dig., 2008, pp. 1-5.
23. C. L. Royer and F. Mayer, "Exhaustive experimental study of tunnel field effect transistors (TFETs): From materials to architecture," in Proc. 10th Int. Conf. ULIS, Mar. 2009, pp. 54-56.
24. P. F. Guo, L. T. Yang, Y. Yang, L. Fan, G. Q. Han, G. S. Samudra, and Y. C. Yeo, "Tunneling field-effect transistor: Effect of strain and temperature on tunneling current," IEEE Electron Device Lett., vol.30, no.9, pp. 981-983, Sep. 2009.
25. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, "Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope," in IEDM Tech. Dig., Dec. 2008, pp. 1-3.
26. P. F. Wang, T. Nirschl, D. S. Landsiedel, and W. Hansch, "Simulation of the Esaki-tunneling FET," Solid State Electron., vol.47, no.7, pp. 1187-1192, Jul. 2003.
27. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering," IEEE Trans. Electron Devices, vol.52, no.5, pp. 909-917, May 2005. (Pubitemid 40690912)
28. K. K. Bhuwalka, J. Schulze, and I. Eisele, "A simulation approach to optimize the electrical parameters of a vertical tunnel FET," IEEE Trans. Electron Devices, vol.52, no.7, pp. 1541-1547, Jul. 2005. (Pubitemid 41194391)
29. M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, "Fringing-induced drain current improvement in the tunnel field-effect transistor with high-k gate dielectrics," IEEE Trans. Electron Devices, vol.56, no.1, pp. 100-108, Jan. 2009.
30. Semiconductor Industry Association (SIA), 2009 Edition International Technology Roadmap for Semiconductors.
31. B. C. Paul, S. Fujita, M. Okajima, T. H. Lee, H. S. P. Wong, and Y. Nishi, "Impact of a process variation on nanowire and nanotube device performance," IEEE Trans. Electron Devices, vol.54, no.9, pp. 2369-2376, Sep. 2007. (Pubitemid 351485752)
32. M. Alam, K. Kang, B. C. Paul, and K. Roy, "Reliability-and processvariation aware design of VLSI circuits," in Proc. 14th IPFA, Bangalore, India, 2007. (Pubitemid 351306656)
33. A. A. M. Bsoul, N. Manjikian, and L. Shang, "Reliability-and process variation-aware placement for FPGAs," in Proc. Des. Autom. Test Eur., 2010, p. 1809.
34. C. Zhou, D. Sylvester, and D. Blaauw, "Process variation and temperatureaware reliability management," in Proc. Des. Autom. Test Eur., 2010, p. 580.
35. Y. Lu, L. Shang, H. Zhou, H. Zhu, F. Yang, and X. Zeng, "Statistical reliability analysis under process variation and aging effects," in Proc. Des. Autom. Conf., San Francisco, CA, Jul. 2009, pp. 514-519.
36. B. P. Harish, N. Bhat, andM. B. Patil, "Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes," Solid State Electron., vol. 50, no. 7/8, pp. 1252-1260, Jul. 2006. (Pubitemid 44232879)
37. A. Mathewson, P. O. Sullivan, A. Concannon, S. Foley, S. Minehane, R. Duane, and K. Palser, "Modelling and simulation of reliability for design," Microelectron. Eng., vol. 49, no. 1/2, pp. 95-117, Nov. 1999. (Pubitemid 30507059)
38. ATLAS User's Manual, Silvaco Int., Santa Clara, CA, Mar. 2, 2007.
39. S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol.50, no.11, pp. 2255-2261, Nov. 2003.
40. T. Ohtou, N. Sugii, and T. Hiramoto, "Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFETs with extremely thin BOX," IEEE Electron Device Lett., vol.28, no.8, pp. 740-742, Aug. 2007. (Pubitemid 47242038)
41. H. R. Khan, D. Mamaluy, and D. Vasileska, "Simulation of the impact of process variation on the optimized 10-nm FinFET," IEEE Trans. Electron Devices, vol.55, no.8, pp. 2134-2141, Aug. 2008.
42. R. Singh, R. Paily, A. Dasgupta, P. Misra, and L. M. Kukreja, "Laser induced oxidation for growth of ultrathin gate oxide," Electron. Lett., vol.40, no.25, pp. 1606-1608, Dec. 2004. (Pubitemid 40021039)
43. A. Nakajima, T. Yoshimoto, T. Kidera, and S. Yokoyama, "Lowtemperature formation of silicon nitride gate dielectrics by atomic-layer deposition," Appl. Phys. Lett., vol.79, no.5, pp. 665-667, Jul. 2001. (Pubitemid 33606903)
44. D. W. McNeill, S. Bhattacharya, H. Wadsworth, F. H. Ruddell, S. J. N. Mitchell, B. M. Armstrong, and H. S. Gamble, "Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates," J. Mater. Sci., Mater. Electron., vol.19, no.2, pp. 119-123, Feb. 2008. (Pubitemid 351149549)
45. W. J. Gross, D. Vasileska, and D. K. Ferry, "Ultrasmall MOSFETs: The importance of the full coulomb interaction on device characteristics," IEEE Trans. Electron Devices, vol.47, no.10, pp. 1831-1837, Oct. 2000. (Pubitemid 34079780)
46. A. Martinez, J. R. Barker, A. Svizhenko, M. P. Anantram, and A. Asenov, "The impact of random dopant aggregation in source and drain on the performance of ballistic DG nano-MOSFETs: A NEGF study," IEEE Trans. Nanotechnol., vol.6, no.4, pp. 438-445, Jul. 2007. (Pubitemid 47153421)
47. H. Yin, K. D. Hobart, R. L. Peterson, F. J. Kub, S. R. Shieh, T. S. Duffy, and J. C. Sturm, "Fully-depleted strained-Si on Insulator NMOSFETs without relaxed SiGe buffers," in IEDM Tech. Dig., 2003, pp. 3.2.1-3.2.4.
48. K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, "Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs," in IEDM Tech. Dig., 2003, pp. 3.1.1-3.1.4.
49. S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, and T. Maeda, "Fabrication and device characteristics of strained-Si-on-insulator (strained SOI) CMOS," Appl. Surf. Sci., vol.224, no.1-4, pp. 241-247, Mar. 2004.
50. T. Numata, T. Mizuno, T. Tezuka, J. Koga, and S. Takagi, "Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices," IEEE Trans. Electron Devices, vol.52, no.8, pp. 1780-1786, Aug. 2005. (Pubitemid 41100640)
51. J. S. Lim, S. E. Thompson, and J. G. Fossum, "Comparison of threshold voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs," IEEE Electron Device Lett., vol.25, no.11, pp. 731-733, Nov. 2004.
52. W. Zhang and J. G. Fossum, "On the threshold voltage of strained-Si-Si1xGex MOSFETs," IEEE Trans. Electron Devices, vol.52, no.2, pp. 263-268, Feb. 2005.
53. S. Dhar, H. Kosina, V. Palankovski, S. E. Ungersboeck, and S. Selberherr, "Electron mobility model for strained-Si devices," IEEE Trans. Electron Devices, vol.52, no.4, pp. 527-533, Apr. 2005. (Pubitemid 40535878)
54. C. Sandow, J. Knoch, C. Urban, Q. T. Zhao, and S. Mantl, "Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors," Solid State Electron., vol.53, no.10, pp. 1126-1129, Oct. 2009.
55. Y. B. Hong, Y. Yang, L. T. Yang, G. Samudra, C. H. Heng, and Y. C. Yeo, "SPICE behavioral model of the tunneling field-effect transistor for circuit simulation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.56, no.12, pp. 946-950, Dec. 2009.