Fringing-induced drain current improvement in the tunnel field-effect transistor with high-κ gate dielectrics

IEEE Transactions on Electron Devices

Volumn 56, Issue 1, 2009, Pages 100-108

  Schlosser, Martin ^a   Bhuwalka, Krishna K ^a,b   Sauter, Martin ^a   Zilbauer, Thomas ^a   Sulima, Torsten ^a   Eisele, Ignaz ^a  

^a BUNDESWEHR UNIVERSITY MUNICH   (Germany)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Drain current; High ; Inverter delay; Metal oxide semiconductor field effect transistor (MOSFET); Subthreshold slope; Tunnel FET

Indexed keywords

CMOS TECHNOLOGY; DEVICE CHARACTERISTICS; EQUIVALENT OXIDE THICKNESS; FRINGING FIELD EFFECTS; FUTURE APPLICATIONS; INVERTER DELAY; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET); MOS-FET; MOSFETS; ON-CURRENTS; SUBTHRESHOLD SLOPE; TECHNOLOGICAL DEVELOPMENT; THEORETICAL LIMITS; THEORETICAL STUDY; TUNNEL FET; WORKING PRINCIPLES;

CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; DIELECTRIC MATERIALS; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; GATES (TRANSISTOR); MESFET DEVICES; MOSFET DEVICES; SILICON COMPOUNDS; SILICON OXIDES; TECHNOLOGICAL FORECASTING; WIND TUNNELS;

DRAIN CURRENT;

EID: 67650671799     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2008375     Document Type: Article

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