-
1
-
-
0004459076
-
-
J. Quinn, et al., Surface Science, Vol. 73, 1978, pp. 190-196.
-
(1978)
Surface Science
, vol.73
, pp. 190-196
-
-
Quinn, J.1
-
2
-
-
0023400490
-
A New Three-Terminal Tunnel Device
-
S. Banerjee, et al., "A New Three-Terminal Tunnel Device", IEEE Elec. Dev. Lett., Vol. 8, 1987, pp. 347-349.
-
(1987)
IEEE Elec. Dev. Lett
, vol.8
, pp. 347-349
-
-
Banerjee, S.1
-
4
-
-
34547850370
-
Tunneling Field-Effect Transistor (TFETs) With Subthreshold Swing (SS) Less Than 60mV/dec
-
W.Y. Choi, et al., "Tunneling Field-Effect Transistor (TFETs) With Subthreshold Swing (SS) Less Than 60mV/dec", IEEE Elec. Dev. Lett., vol. 28, no. 8, 2007, pp. 743-745.
-
(2007)
IEEE Elec. Dev. Lett
, vol.28
, Issue.8
, pp. 743-745
-
-
Choi, W.Y.1
-
5
-
-
67650618284
-
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope
-
T. Krishnamohan, et al., "Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope", Proc. of IEDM, 2008, pp.947-949.
-
(2008)
Proc. of IEDM
, pp. 947-949
-
-
Krishnamohan, T.1
-
6
-
-
33646900772
-
P-channel tunnel field-effect transistors down to sub-50 nm channel lengths
-
K. Bhuwalka, et al., "P-channel tunnel field-effect transistors down to sub-50 nm channel lengths," Jpn. J. Appl. Phys., Vol. 45, no. 4B, pp. 3106-3109, 2006.
-
(2006)
Jpn. J. Appl. Phys
, vol.45
, Issue.4 B
, pp. 3106-3109
-
-
Bhuwalka, K.1
-
7
-
-
67650671799
-
Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High-κ Gate Dielectrics
-
Jan
-
M. Schlosser, et al., "Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High-κ Gate Dielectrics", IEEE TED., Vol. 56, No 1, Jan. 2009, pp.100-108.
-
(2009)
IEEE TED
, vol.56
, Issue.1
, pp. 100-108
-
-
Schlosser, M.1
-
8
-
-
67650683613
-
xOI and GeOI substrates on CMOS compatible Tunnel FET performance
-
xOI and GeOI substrates on CMOS compatible Tunnel FET performance", Proc. of IEDM, 2008, pp. 163-166.
-
(2008)
Proc. of IEDM
, pp. 163-166
-
-
Mayer, F.1
-
9
-
-
4544248640
-
Complementary tunneling transistor for low power application
-
May
-
P.-F. Wang, et al., "Complementary tunneling transistor for low power application", Solid States Electronics, Vol. 48, May 2004.
-
(2004)
Solid States Electronics
, vol.48
-
-
Wang, P.-F.1
-
10
-
-
19744366972
-
Band-to-band tunneling in carbon nanotube field-effect transistors
-
Phys. Rev. Lett, 196805-4, Nov
-
J. Appenzeller, et al., "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., Vol. 93, No 19, pp. 196805-1 - 196805-4, Nov. 2004.
-
(2004)
, vol.93
, Issue.19
, pp. 196805-196811
-
-
Appenzeller, J.1
-
11
-
-
34547697110
-
Tunnel field-effect transistor without gate-drain overlap
-
A. Verhulst et al., "Tunnel field-effect transistor without gate-drain overlap", Appl. Phys. Lett. 91, 053102 (2007).
-
(2007)
Appl. Phys. Lett
, vol.91
, pp. 053102
-
-
Verhulst, A.1
-
12
-
-
34447321846
-
Double-Gate Tunnel FET With High-κ Gate Dielectric
-
July
-
K. Boucart et al., "Double-Gate Tunnel FET With High-κ Gate Dielectric", IEEE TED, Vol. 54, No 7, July 2007, p. 1725-1733.
-
(2007)
IEEE TED
, vol.54
, Issue.7
, pp. 1725-1733
-
-
Boucart, K.1
-
13
-
-
54749153664
-
-
A. Verhulst et al., Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization, Journal of Applied Physics, 104, pp. 064514-1 - 064514-10 (2008).
-
A. Verhulst et al., "Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization", Journal of Applied Physics, Vol. 104, pp. 064514-1 - 064514-10 (2008).
-
-
-
-
14
-
-
54249110984
-
Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon-Germanium Source
-
E.-H. Toh, et al., "Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon-Germanium Source", Jpn. J. Appl. Phys. 47 (2008) pp. 2593-2597.
-
(2008)
Jpn. J. Appl. Phys
, vol.47
, pp. 2593-2597
-
-
Toh, E.-H.1
-
15
-
-
34247247817
-
Fabrication of SiGe-on-insulator substrates by a condensation technique: An experimental and modelling study
-
B. Vincent et al., "Fabrication of SiGe-on-insulator substrates by a condensation technique: an experimental and modelling study", Semicond. Sci. Technol., 22, 237, (2007).
-
(2007)
Semicond. Sci. Technol
, vol.22
, pp. 237
-
-
Vincent, B.1
-
16
-
-
84957890418
-
Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS
-
F. Mayer, et al., "Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS", Proc. of ESSDERC, 2006, pp. 303-306.
-
(2006)
Proc. of ESSDERC
, pp. 303-306
-
-
Mayer, F.1
-
17
-
-
58049121341
-
High performance 70nm gate length Germanium-On-Insulator pMOSFET with high- /metal gate
-
K. Romanjek et al., "High performance 70nm gate length Germanium-On-Insulator pMOSFET with high- /metal gate", Proc. of ESSDERC 2008, pp. 75-78.
-
(2008)
Proc. of ESSDERC
, pp. 75-78
-
-
Romanjek, K.1
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