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Volumn 47, Issue 7 SPEC., 2003, Pages 1187-1192

Simulation of the Esaki-tunneling FET

Author keywords

Esaki tunneling FET; MOSFET; Simulation; Zener tunneling

Indexed keywords

COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRON TUNNELING; MOS DEVICES; SILICON; THRESHOLD VOLTAGE;

EID: 0038417912     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00045-5     Document Type: Conference Paper
Times cited : (40)

References (7)
  • 1
    • 0034453372 scopus 로고    scopus 로고
    • 50-nm vertical sidewall transistors with high channel doping concentrations
    • Schulz T., Rösner W., Risch L., Langmann U. 50-nm vertical sidewall transistors with high channel doping concentrations. IEDM. 2000;61-64.
    • (2000) IEDM , pp. 61-64
    • Schulz, T.1    Rösner, W.2    Risch, L.3    Langmann, U.4
  • 2
    • 0033887194 scopus 로고    scopus 로고
    • A 20-nm physical gate length NMOSFET featuring 1.2-nm gate oxide, shallow implanted source and drain and BF2 pockets
    • Deleonibus S., Caillat C., Guegan G.et al. A 20-nm physical gate length NMOSFET featuring 1.2-nm gate oxide, shallow implanted source and drain and BF2 pockets. IEEE Electron Device Lett. 21(12):2000;173-175.
    • (2000) IEEE Electron Device Lett. , vol.21 , Issue.12 , pp. 173-175
    • Deleonibus, S.1    Caillat, C.2    Guegan, G.3
  • 5
    • 0034225075 scopus 로고    scopus 로고
    • A vertical MOS-gated Esaki tunneling transistor in silicon
    • Hansch W., Fink C., Schulze J., Eisele I. A vertical MOS-gated Esaki tunneling transistor in silicon. Thin Solid Films. 369:2000;387-389.
    • (2000) Thin Solid Films , vol.369 , pp. 387-389
    • Hansch, W.1    Fink, C.2    Schulze, J.3    Eisele, I.4
  • 7
    • 50549156338 scopus 로고
    • Zener tunneling in semiconductors
    • Kane E.O. Zener tunneling in semiconductors. J. Phys. Chem. Solids. 12:1959;181-188.
    • (1959) J. Phys. Chem. Solids , vol.12 , pp. 181-188
    • Kane, E.O.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.