Reliability- and process variation-aware placement for FPGAs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 1809-1814

  Bsoul, Assem A M ^a   Manjikian, Naraig ^b   Shang, Li ^c  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b QUEEN S UNIVERSITY   (Canada)

^c UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; NEGATIVE BIAS TEMPERATURE INSTABILITY; THRESHOLD VOLTAGE;

CIRCUIT PERFORMANCE; DELAY ESTIMATION; EMBEDDED FPGA; LOW OVERHEAD; PROCESS VARIATION; REGION-BASED; RUN-TIME PERFORMANCE; TIMING ANALYSIS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77953097556     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457107     Document Type: Conference Paper

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