Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

Solid-State Electronics

Volumn 50, Issue 7-8, 2006, Pages 1252-1260

  Harish, B P ^a   Bhat, Navakanta ^a   Patil, Mahesh B ^b  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Analytical modeling; Delay distribution; Mixed mode simulations; Monte Carlo analysis; Process sensitivity

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC CURRENTS; GATES (TRANSISTOR); INTERPOLATION; MATHEMATICAL MODELS; MONTE CARLO METHODS; NAND CIRCUITS;

ANALYTICAL MODELING; DELAY DISTRIBUTION; MIXED-MODE SIMULATION; MONTE CARLO ANALYSIS; PROCESS SENSITIVITY;

CMOS INTEGRATED CIRCUITS;

EID: 33747162160     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.07.005     Document Type: Article

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