-
1
-
-
1842516472
-
"First observation of negative differential resistance in surface tunnel transistor"
-
T. Uemura and T. Baba, "First observation of negative differential resistance in surface tunnel transistor," Jpn. J. Appl. Phys., vol. 33, no. 2B. pp. L207-L210, 1994.
-
(1994)
Jpn. J. Appl. Phys.
, vol.33
, Issue.2 B
-
-
Uemura, T.1
Baba, T.2
-
2
-
-
0007981204
-
"Negative differential conductance in three-terminal silicon tunneling device"
-
J. Koga and A. Toriumi, "Negative differential conductance in three-terminal silicon tunneling device," Appl. Phys. Lett., vol. 69, no. 10, pp. 1435-1437, 1996.
-
(1996)
Appl. Phys. Lett.
, vol.69
, Issue.10
, pp. 1435-1437
-
-
Koga, J.1
Toriumi, A.2
-
3
-
-
1842464239
-
"Negative differential conductance at room temperature in three-terminal silicon surface junction tunneling device"
-
J. Koga and A. Toriumi, "Negative differential conductance at room temperature in three-terminal silicon surface junction tunneling device," Appl. Phys. Lett., vol. 70, no. 16, pp. 2138-2140, 1997.
-
(1997)
Appl. Phys. Lett.
, vol.70
, Issue.16
, pp. 2138-2140
-
-
Koga, J.1
Toriumi, A.2
-
4
-
-
0033341645
-
"Three-terminal silicon surface junction tunneling device for room temperature operation"
-
J. Koga and A. Toriumi, "Three-terminal silicon surface junction tunneling device for room temperature operation," IEEE Electron Device Lett., vol. 20, no. 10, pp. 529-531, Oct. 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, Issue.10
, pp. 529-531
-
-
Koga, J.1
Toriumi, A.2
-
5
-
-
3643062973
-
"Silicon surface tunnel transistor"
-
W. M. Reddick and G. A. J. Amaratunga, "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, no. 4, pp. 494-497, 1995.
-
(1995)
Appl. Phys. Lett.
, vol.67
, Issue.4
, pp. 494-497
-
-
Reddick, W.M.1
Amaratunga, G.A.J.2
-
6
-
-
1842581409
-
"Lateral interband tunneling transistor in silicon-on-insulator"
-
C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, "Lateral interband tunneling transistor in silicon-on-insulator," Appl. Phys. Lett., vol. 84, no. 10, pp. 1780-1782, 2004.
-
(2004)
Appl. Phys. Lett.
, vol.84
, Issue.10
, pp. 1780-1782
-
-
Aydin, C.1
Zaslavsky, A.2
Luryi, S.3
Cristoloveanu, S.4
Mariolle, D.5
Fraboulet, D.6
Deleonibus, S.7
-
7
-
-
0034225075
-
"A vertical MOS-gated Esaki tunneling transistor in silicon"
-
W. Hansch, C. Fink, J. Schulze, and I. Eisele, "A vertical MOS-gated Esaki tunneling transistor in silicon," Thin Solid Films, vol. 369, pp. 387-389, 2000.
-
(2000)
Thin Solid Films
, vol.369
, pp. 387-389
-
-
Hansch, W.1
Fink, C.2
Schulze, J.3
Eisele, I.4
-
8
-
-
0035328742
-
"Performance improvement in vertical surface tunneling transistors by a boron surface phase"
-
W. Hansch, P. Borthen, J. Schulze, C. Fink, T. Sulima, and I. Eisele, "Performance improvement in vertical surface tunneling transistors by a boron surface phase," Jpn. J. Appl Phys, vol. 40, no. 5A, pp. 3131-3136, 2001.
-
(2001)
Jpn. J. Appl Phys
, vol.40
, Issue.5 A
, pp. 3131-3136
-
-
Hansch, W.1
Borthen, P.2
Schulze, J.3
Fink, C.4
Sulima, T.5
Eisele, I.6
-
9
-
-
0037074829
-
"Phonon assisted tunneling in gated p-i-n diodes"
-
S. Sedlmaier, J. Schulze, T. Sulima, C. Fink, C. Tolksdorf, A. Bayer-stadler, I. Eisele, P.-F. Wang, K. Hilsenbeck, and W. Hansch, "Phonon assisted tunneling in gated p-i-n diodes," Mater. Sci. Eng., vol. B89, no. 1-3, pp. 116-119, 2002.
-
(2002)
Mater. Sci. Eng.
, vol.B89
, Issue.1-3
, pp. 116-119
-
-
Sedlmaier, S.1
Schulze, J.2
Sulima, T.3
Fink, C.4
Tolksdorf, C.5
Bayer-Stadler, A.6
Eisele, I.7
Wang, P.-F.8
Hilsenbeck, K.9
Hansch, W.10
-
10
-
-
0024862571
-
"Quantized states in delta-doped Si layers"
-
I. Eisele, "Quantized states in delta-doped Si layers," Superlatt. Microstruct., vol. 6, no. 1, pp. 123-128, 1989.
-
(1989)
Superlatt. Microstruct.
, vol.6
, Issue.1
, pp. 123-128
-
-
Eisele, I.1
-
11
-
-
18844407391
-
"Vertical tunnel FET grown by MBE"
-
Sante Fe, NM
-
S. Sedlmaier, K. K. Bhuwalka, A. Ludsteck, J. Schulze, W. Hansch, and I. Eisele, "Vertical tunnel FET grown by MBE," in Proc. ICS13, Int. Conf. on SiGe(C) Epitaxy and Heterostructures, Sante Fe, NM, 2003, pp. 226-229.
-
(2003)
Proc. ICS13, Int. Conf. on SiGe(C) Epitaxy and Heterostructures
, pp. 226-229
-
-
Sedlmaier, S.1
Bhuwalka, K.K.2
Ludsteck, A.3
Schulze, J.4
Hansch, W.5
Eisele, I.6
-
12
-
-
0442279707
-
"Vertical tunnel field-effect transistor"
-
K. K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279-282, 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.2
, pp. 279-282
-
-
Bhuwalka, K.K.1
Sedlmaier, S.2
Ludsteck, A.3
Tolksdorf, C.4
Schulze, J.5
Eisele, I.6
-
13
-
-
4644251010
-
+ layer"
-
+ layer," Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, 2004.
-
(2004)
Jpn. J. Appl. Phys.
, vol.43
, Issue.7 A
, pp. 4073-4078
-
-
Bhuwalka, K.K.1
Schulze, J.2
Eisele, I.3
-
14
-
-
4944232119
-
"Gate-controlled resonant interband tunneling in silicon"
-
S. Sedlmaier, K. K. Bhuwalka, A. Ludsteck, M. Schmidt, J. Schulze, W. Hansch, and I. Eisele, "Gate-controlled resonant interband tunneling in silicon," Appl. Phys. Lett., vol. 85, no. 10, pp. 1707-1709, 2004.
-
(2004)
Appl. Phys. Lett.
, vol.85
, Issue.10
, pp. 1707-1709
-
-
Sedlmaier, S.1
Bhuwalka, K.K.2
Ludsteck, A.3
Schmidt, M.4
Schulze, J.5
Hansch, W.6
Eisele, I.7
-
15
-
-
18844400435
-
-
Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS)
-
Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2001.
-
(2001)
-
-
-
17
-
-
50549156338
-
"Zener tunneling in semiconductor"
-
E. O. Kane, "Zener tunneling in semiconductor," J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, 1959.
-
(1959)
J. Phys. Chem. Solids
, vol.12
, Issue.2
, pp. 181-188
-
-
Kane, E.O.1
-
19
-
-
0038417912
-
"Simulation of the Esaki-tunneling FET"
-
P. F. Wang, T. Nirschl, D. S-Landsiedel, and W. Hansch, "Simulation of the Esaki-tunneling FET," Solid-State Electron., vol. 47, no. 7, pp. 1187-1193, 2003.
-
(2003)
Solid-State Electron.
, vol.47
, Issue.7
, pp. 1187-1193
-
-
Wang, P.F.1
Nirschl, T.2
S-Landsiedel, D.3
Hansch, W.4
-
20
-
-
0343759851
-
1-x/Si heterostructures: The structural stability of buried strained layers and strained-layer superlattices"
-
1-x/Si heterostructures: The structural stability of buried strained layers and strained-layer superlattices," J. Appl. Phys., vol. 67, no. 4, pp. 1850-1862, 1990.
-
(1990)
J. Appl. Phys.
, vol.67
, Issue.4
, pp. 1850-1862
-
-
Houghton, D.C.1
Perovic, D.D.2
Baribean, J.M.3
Weatherly, G.C.4
-
21
-
-
17644425184
-
+ SiGe layer"
-
Notre Dame, IN, Jun. 21-23
-
+ SiGe layer," in Proc. 62nd Device Research Conf., Notre Dame, IN, Jun. 21-23, 2004, pp. 215-216.
-
(2004)
Proc. 62nd Device Research Conf.
, pp. 215-216
-
-
Bhuwalka, K.K.1
Schulze, J.2
Eisele, I.3
-
23
-
-
0036508274
-
"Power-constrained CMOS scaling limits"
-
D. J. Frank, "Power-constrained CMOS scaling limits," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 235-244, 2002.
-
(2002)
IBM J. Res. Develop.
, vol.46
, Issue.2-3
, pp. 235-244
-
-
Frank, D.J.1
-
24
-
-
17644379098
-
"Vertical tunnel field-effect transistor with bandgap modulation and workfunction engineering"
-
Leuven, Belgium, Sep. 21-23
-
K. K. Bhuwalka, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor with bandgap modulation and workfunction engineering," in Proc. 34th Eur. Solid State Device Research Conf., Leuven, Belgium, Sep. 21-23, 2004, pp. 241-244.
-
(2004)
Proc. 34th Eur. Solid State Device Research Conf.
, pp. 241-244
-
-
Bhuwalka, K.K.1
Schulze, J.2
Eisele, I.3
-
25
-
-
0026237465
-
x gate material for submicrometer CMOS technologies"
-
Oct
-
x gate material for submicrometer CMOS technologies," IEEE Electron Device Lett., vol. 12, no. 10, pp. 533-535, Oct. 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, Issue.10
, pp. 533-535
-
-
King, T.-J.1
Pfiester, J.R.2
Saraswat, K.C.3
-
26
-
-
13444310993
-
"Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications"
-
Feb
-
J. Yuan and J. C. S. Woo, "Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications," IEEE Electron. Device Let., vol. 26, no. 2, pp. 87-89, Feb. 2005.
-
(2005)
IEEE Electron. Device Let.
, vol.26
, Issue.2
, pp. 87-89
-
-
Yuan, J.1
Woo, J.C.S.2
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