Simulation of the impact of process variation on the optimized 10-nm FinFET

IEEE Transactions on Electron Devices

Volumn 55, Issue 8, 2008, Pages 2134-2141

  Khan, Hasanur R ^a   Mamaluy, Denis ^a   Vasileska, Dragica ^a  

^a Arizona State University   (United States)

Author keywords

Contact block reduction (CBR) method; FinFET; Process variation; Quantum transport; Slow corner analysis

Indexed keywords

DRAIN CURRENT; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; GATES (TRANSISTOR); INDUCED CURRENTS; MOS CAPACITORS; MOSFET DEVICES; NONMETALS; OPTIMIZATION; POLYSILICON; QUANTUM CHEMISTRY; SENSITIVITY ANALYSIS; SILICON; SILICON CARBIDE; SULFATE MINERALS;

AND GATES; CONTACT BLOCK REDUCTION (CBR) METHOD; CONTACT BLOCK REDUCTION METHOD; DEVICE PERFORMANCES; DRAIN LEAKAGE CURRENT; DRAIN-INDUCED BARRIER LOWERING; FINFET; GATE LEAKAGES; GATE OXIDE THICKNESS; GATE-LEAKAGE CURRENTS; ON CURRENTS; PERFORMANCE MATRICES; POLY-SI GATES; PROCESS VARIATION; PROCESS VARIATIONS; QUANTUM TRANSPORT; QUANTUM-MECHANICAL; ROOM TEMPERATURES; SENSITIVE PARAMETER; SILICON CARBIDE DEVICES; SLOW CORNER ANALYSIS; SUB THRESHOLDS; SUB-THRESHOLD SWING; WORK FUNCTIONS; WORST CASE;

LEAKAGE CURRENTS;

EID: 49249119323     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.925937     Document Type: Article

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