Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Mayer, F ^a   Le Royer, C ^a   Damlencourt, J F ^a   Romanjek, K ^a   Andrieu, F ^a   Tabone, C ^a   Previtali, B ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS DEVICES; CMOS-COMPATIBLE; CONTINUOUS IMPROVEMENTS; EXPERIMENTAL INVESTIGATIONS; FULLY DEPLETED SOI; GE CONTENTS; METAL GATE STACKS; ON CURRENTS; PARASITIC CONDUCTIONS; PROCESS FLOWS; SOURCE DRAINS; STATE CONTROLS; TUNNEL FETS;

ELECTRON DEVICES; FIELD EFFECT TRANSISTORS; MESFET DEVICES; MOSFET DEVICES; SILICON; SILICON ON INSULATOR TECHNOLOGY; TUNNELS;

GERMANIUM;

EID: 64549144144     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796641     Document Type: Conference Paper

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