SPICE behavioral model of the tunneling field-effect transistor for circuit simulation

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 56, Issue 12, 2009, Pages 946-950

  Hong, Yibin ^a   Yang, Yue ^a   Yang, Litao ^a   Samudra, Ganesh ^a   Heng, Chun Huat ^a   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Behavioral modeling; Inverter; SPICE simulation; Tunneling field effect transistor (TFET)

Indexed keywords

BEHAVIORAL RESEARCH; CAPACITANCE; ELECTRONIC DESIGN AUTOMATION; INTEGRATED CIRCUIT MANUFACTURE; TIMING CIRCUITS; TUNNEL FIELD EFFECT TRANSISTORS;

BEHAVIORAL MODEL; DEEP SUBMICROMETER; INVERTER; IV CHARACTERISTICS; PARASITIC CAPACITANCE; SPICE SIMULATIONS; TECHNOLOGY COMPUTER AIDED DESIGN; TUNNELING FIELD-EFFECT TRANSISTORS;

SPICE;

EID: 73149123341     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2009.2035274     Document Type: Article

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