A simulation approach to optimize the electrical parameters of a vertical tunnel FET

IEEE Transactions on Electron Devices

Volumn 52, Issue 7, 2005, Pages 1541-1547

  Bhuwalka, Krishna Kumar ^a   Schulze, Jörg ^a   Eisele, Ignaz ^a  

^a BUNDESWEHR UNIVERSITY MUNICH   (Germany)

Author keywords

Band to band tunneling; Gated p i n diode; Heterostructure; Kane's model; SiGe; Subthreshold swing; Surface tunneling FET; Threshold voltage; Vertical tunnel field effect transistor; Zener tunneling

Indexed keywords

COMPUTER SIMULATION; ELECTRON TUNNELING; GATES (TRANSISTOR); HETEROJUNCTIONS; MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DIODES; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; ZENER EFFECT;

BAND-TO-BAND TUNNELING; GATED P-I-N DIODE; KANE MODEL; SUBTHRESHOLD SWING; SURFACE TUNNELING FET; VERTICAL TUNNEL FIELD EFFECT TRANSISTOR; ZENER TUNNELING;

FIELD EFFECT TRANSISTORS;

EID: 23944478215     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.850618     Document Type: Article

References (28)

1. T. Uemura and T. Baba, "First observation of negative differential resistance in surface tunnel transistor," Jpn. J. Appl. Phys., vol. 33, no. 2B, pp. L207-L210, 1994.
2. J. Koga and A. Toriumi, "Negative differential conductance in three-terminal Silicon tunneling device," Appl. Phys. Lett., vol. 69, no. 10, pp. 1435-1437, 1996.
3. J. Koga and A. Toriumi, "Negative differential conductance at room temperature in three-terminal silicon surface junction tunneling device," Appl. Phys. Lett., vol. 70, no. 16, pp. 2138-2140, 1997.
4. J. Koga and A. Toriumi, "Three-Terminal Silicon surface junction tunneling device for room temperature operation," IEEE Electron Device Lett., vol. 20, no. 10, pp. 529-531, Oct. 1999.
5. W. M. Reddick and G. A. J. Amaratunga, "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, no. 4, pp. 494-497, 1995.
6. W. Hansch, C. Fink, J. Schulze, and I. Eisele, "A vertical MOS-gated Esaki tunneling transistor in Silicon," Thin Solid Films, vol. 369, no. 1-2, pp. 387-389, 2000.
7. W. Hansch, P. Borthen, J. Schulze, C. Fink, T. Sulima, and I. Eisele, "Performance improvement in vertical surface tunneling transistors by a boron surface phase," Jpn. J. Appl Phys, vol. 40, no. 5A, pp. 3131-3136, 2001.
8. S. Sedlmaier, J. Schulze, T. Sulima, C. Fink, C. Tolksdorf, A. Bayerstadler, I. Eisele, P.-F. Wang, K. Hilsenbeck, and W. Hansch, "Phonon assisted tunnneling in gated p-i-n diodes," Mater. Sci. Eng., vol. B89, no. 1-3, pp. 116-119, 2002.
9. C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, "Lateral interband tunneling transistor in silicon-on-insulator," Appl. Phys. Letters, vol. 84, no. 10, pp. 1780-1782, 2004.
10. K. K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279-282, Feb. 2004.
11. S. Sedlmaier, K. K. Bhuwalka, A. Ludsteck, M. Schmidt, J. Schulze, W. Hansch, and I. Eisele, "Gate-controlled resonant interband tunneling in Silicon," Appl. Phys. Letters, vol. 85, no. 10, pp. 1707-1709, 2004.
12. + Layer," Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, 2004.
13. P. F. Wang, T. Nirschl, D. S-Landsiedel, and W. Hansch, "Simulation of the Esaki-tunneling FET," Solid State Electron., vol. 47, no. 7, pp. 1187-1193, 2003.
14. + SiGe Layer, in Proc. 62nd Device Research Conf., Norte Dame, Indiana, June, 21-23 2004, pp. 215-216.
15. E. O. Kane, "Zener tunneling in semiconductor," J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, 1960.
16. MEDICI User's Manual Version 2001.2 (2000).
17. W. M. Reddick and G. A. J. Amaratunga, "Gate controlled surface tunneling transistor," in Proc. High Speed Semiconductor Dev. Circuits, Aug., 7-9 1995, pp. 490-497.
18. J.-C. Gui, Y.-C. Lou, M. H. Chou, M. T. Wang, and F. Shone, "A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET," IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1518-1523, Jul. 1998.
19. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 497.
20. J.-H. Chen, S.-C. Wong, and Y.-H. Wang, "An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET," IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1400-1405, Jul. 2001.
21. K.-F. You and C.-Y. Wu, "A new quasi-2-D model for hot-carrier band-to-band tunneling current," IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1174-1179, 1999.
22. S. Banerjee, W. Richardson, J. Coleman, and A. Chatterjee, "A new three-terminal tunnel device," IEEE Electron Device Lett., vol. 8, no. 8, pp. 347-349, Aug. 1987.
23. E. O. Kane, "Theory of tunneling," J. Appl. Phys., vol. 32, no. 1, pp. 83-91, 1961.
24. M. Takayanagi and S. Iwabuchi, "Theory of band-to-band tunneling under nonuniform electric fields for subthreshold leakage currents," IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1425-1431, Jun. 1991.
25. C. Rivas, R. Lake, G. Klimeck, W. R. Frensley, M. V. Fischetti, P. E. Thompson, S. L. Rommel, and P. R. Berger, "Full-band simulation of indirect phonon assisted tunneling in a silicon tunnel diode with delta-doped contacts," Appl. Phys. Lett., vol. 78, no. 6, pp. 814-817, 2001.
26. P. M. Solomon, J. Jopling, D. J. Frank, C. D'Emic, O. Dokumaci, P. Ronsheim, and W. E. Haensch, "Universal tunneling behavior in technologically relevant P/N junction diodes," J. Appl. Phys., vol. 95, no. 10, pp. 5800-5812, 2004.
27. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor with bandgap modulation and workfunction engineering," in Proc. 34th Eur. Solid-State Device Research Conf., Leuven, Belgium, Sep., 21-23 2004, pp. 241-244.
28. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel field-effect transistor with tunnel bandgap modulation and gate workfunction engineering," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909-917, May 2005.