Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 2, 2009, Pages 147-162

  Kerber, Andreas ^a   Cartier, Eduard Albert ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b IBM RESEARCH   (United States)

Author keywords

Bias temperature instability; Dielectric breakdown; HfO2; High k; Metal gate; MOSFETs; Reliability; Stress induced leakage current (SILC); TiN

Indexed keywords

BIAS TEMPERATURE INSTABILITY; DIELECTRIC BREAKDOWN; HFO2; HIGH-K; METAL GATE; MOSFETS; STRESS INDUCED LEAKAGE CURRENT (SILC);

CHARGE TRAPPING; CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ELECTRIC PROPERTIES; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; LOGIC GATES; MOSFET DEVICES; NITRIDES; RELIABILITY; TITANIUM COMPOUNDS; TITANIUM NITRIDE;

HAFNIUM COMPOUNDS;

EID: 67650418339     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2009.2016954     Document Type: Article

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