High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 194-195

  Chudzik, M ^a   Doris, B ^b   Mo, R ^b   Sleight, J ^b   Cartier, E ^b   Dewan, C ^b   Park, D ^b   Bu, H ^b   Natzle, W ^b   Yan, W ^a   Ouyang, C ^b   Henson, K ^a   Boyd, D ^a   Callegari, S ^b   Carter, R ^c   Casarotto, D ^a   Gribelyuk, M ^a   Hargrove, M ^c   He, W ^a   Kim, Y ^b   Linder, B ^b   Moumen, N ^a   Paruchuri, V K ^b   Stathis, J ^b   Steen, M ^b   Vayshenker, A ^a   Wang, X ^b   Zafar, S ^b   Ando, T ^b   Iijima, R ^b   Takayanagi, M ^b   Narayanan, V ^b   Wise, R ^a   Zhang, Y ^b   Divakaruni, R ^a   Khare, M ^b   Chen, T C ^b   more..

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM NODE; BAND EDGES; DUAL STRESS LINERS; METAL GATES; SHORT CHANNELS; SILICON ON INSULATOR (SOI) SUBSTRATES; VLSI TECHNOLOGIES;

DATA STORAGE EQUIPMENT; NONMETALS; SEMICONDUCTING SILICON COMPOUNDS; SILICON;

METALS;

EID: 36448952970     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339689     Document Type: Conference Paper

References (8)

1. J. Sleight et al., International Electron Devices Meeting (IEDM), San Fran., CA, 2006
2. E. Cartier et al., 2005 Symposium on VLSI Technology, pp. 230-1, 2005
3. J. K. Schaeffer et al., APL, 85, pg. 1826, 2004
4. F. Andrieu et al. International Electron Devices Meeting (IEDM), San Fran., CA, 2006
5. E. Gusev, V. Narayanan, M. Frank, IBM J. Res. & Dev. Vol. 50 (4-5) pp. 387-410 Jul-Sep. 2006
6. V. Narayanan et al., IEEE Elec. Dev. Lett. Vol.27 (7) pp. 591-4, July 2006
7. K. Rim et al., IEDM Technical Digest, pp. 43-6, 2002
8. S. Zafar et al., VLSI Technology Digest, pp. 30-21, 2006