Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 154-155

  Harris, H Rusty ^b   Kalra, Pankaj ^e   Majhi, Prashant ^c   Hussain, Muhammed ^a   Kelly, David ^a   Oh, Jungwoo ^a   He, Dawei ^a   Smith, Casey ^a   Barnett, Joel ^a   Kirsch, Paul D ^d   Gebara, Gabriel ^b   Jur, Jess ^f   Lichtenwalner, Daniel ^f   Lubow, Abigail ^g   Ma, T P ^g   Sung, Guangyu ^h   Thompson, Scott ^h   Lee, Byoung Hun ^d   Tseng, Hsing Huang ^a   Jammy, Raj ^d  

^a SEMATECH   (United States)

^b AMD ^*

^c INTEL CORPORATION   (United States)

^d IBM   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f NORTH CAROLINA STATE UNIVERSITY   (United States)

^g YALE UNIVERSITY   (United States)

^h UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEAL TEMPERATURES; DUAL-CHANNEL SCHEMES; PMOS DEVICES; SHORT CHANNELS; STRAINED SIGE; VLSI TECHNOLOGIES;

LANTHANUM; SILICON; STANDARDS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 37549063505     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339763     Document Type: Conference Paper

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