A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 88-89

  Chen, X ^a   Samavedam, S ^b   Narayanan, V ^a   Stein, K ^a   Hobbs, C ^b   Baiocco, C ^a   Li, W ^a   Jaeger, D ^a   Zaleski, M ^b   Yang, H S ^a   Kim, N ^c   Lee, Y ^a   Zhang, D ^b   Kang, L ^b   Chen, J ^c   Zhuang, H ^d   Sheikh, A ^a   Wallner, J ^a   Aquilino, M ^a   Han, J ^d   Jin, Z ^a   Li, J ^a   Massey, G ^a   Kalpat, S ^a   Jha, R ^a   Moumen, N ^a   Mo, R ^a   Kirshnan, S ^a   Wang, X ^a   Chudzik, M ^a   Chowdhury, M ^b   Nair, D ^a   Reddy, C ^b   Teh, Y W ^c   Kothandaraman, C ^e   Coolbaugh, D ^a   Pandey, S ^c   Tekleab, D ^c   Thean, A ^b   Sherony, M ^a   Lage, C ^b   Sudijono, J ^c   Lindsay, R ^d   Ku, J H ^e   Khare, M ^a   Steegen, A ^a   more..

^a IBM RESEARCH   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c Chartered Semiconductor Manufacturing ^*

^d INFINEON TECHNOLOGIES AG   (Germany)

^e SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; STATIC RANDOM ACCESS STORAGE;

CELL SIZES; CMOS TECHNOLOGIES; HIGH-DENSITY; LOW POWER APPLICATIONS; LOW POWER CMOS; LOW STANDBY LEAKAGE; PLATFORM TECHNOLOGY; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 51949107160     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588573     Document Type: Conference Paper

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7. E. Josse, IEDM 2006, p.693