Challenges and opportunities for high performance 32 nm CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Sleight, J W ^a   Lauer, I ^a   Dokumaci, O ^a   Fried, D M ^a   Guo, D ^a   Haran, B ^a   Narasimha, S ^a   Sheraw, C ^a   Singh, D ^a   Steigerwalt, M ^a   Wang, X ^a   Oldiges, P ^a   Sadana, D ^a   Sung, C Y ^a   Haensch, W ^a   Khare, M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM NODE; CMOS TECHNOLOGIES; CRITICAL PATHS; DEGREE OF FREEDOM; DEVICE ISOLATION; DEVICE PERFORMANCES; GATE LENGTH SCALING; IN-DEPTH ANALYSIS; PARASITICS; RING OSCILLATORS; STRESS ENGINEERING;

COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRON BEAM LITHOGRAPHY; ELECTRON DEVICES; TECHNOLOGY;

NANOTECHNOLOGY;

EID: 46049091002     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346881     Document Type: Conference Paper

References (4)

1. S.D. Kim et al., 6.6, IEDM 2005.
2. S.M. Rossnagel et al., JVST B, p. 2047, 2002.
3. V. Narayanan et al., p. 224, VLSI 2006.
4. M.H. Na et al., IEDM 2002.