Three-dimensional and 2.5 dimensional interconnection technology: State of the art

Journal of Electronic Packaging

Volumn 136, Issue 1, 2014, Pages

  Liu, Dapeng ^a   Park, Seungbae ^a  

^a State University of New York   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT INTERCONNECTS; THREE DIMENSIONAL INTEGRATED CIRCUITS;

EMERGING TECHNOLOGIES; INTERCONNECTION DENSITY; INTERCONNECTION TECHNOLOGY; PACKAGE SIZE; PERFORMANCE; SILICON INTERPOSERS; SMALL PACKAGE; STATE OF THE ART; THREE-DIMENSIONAL (3D) PACKAGING; THROUGH SILICON VIAS;

SILICON WAFERS;

EID: 84894528057     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.4026615     Document Type: Article

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