Wafer bumping, assembly, and reliability assessment of μbumps with 5μm pads on 10μm pitch for 3D IC integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 636-640

  Lee, Ching Kuan ^a   Zhan, Chau Jie ^a   Lau, John H ^a   Huang, Yu Jiau ^a   Fu, Huan Chun ^a   Huang, Jui Hsiung ^a   Hsiao, Zhi Cheng ^a   Chen, Shang Wei ^a   Huang, Shin Yi ^a   Fan, Chia Wen ^a   Lin, Yu Min ^a   Kao, Kuo Shu ^a   Ko, Cheng Ta ^a   Chen, Tai Hung ^a   Lo, Robert ^a   Kao, M J ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROPLATING TECHNIQUE; INTEGRATION APPLICATION; LAYER THICKNESS; LEAD FREE SOLDERS; MICRO-BUMPS; MICROSTRUCTURE ANALYSIS; MOORE'S LAW; ON-WAFER; PAD SIZES; PEAK TEMPERATURES; RELIABILITY ASSESSMENTS; SEED LAYER; SHEAR TESTS; SOLDER COMPOUNDS; SOLDER JOINTS; TEST VEHICLE; THERMO-COMPRESSION; ULTRA FINE PITCH; WAFER BUMPING;

INTERMETALLICS; RELIABILITY ANALYSIS; SOLDERING ALLOYS; THREE DIMENSIONAL COMPUTER GRAPHICS; TIN; WET ETCHING;

WAFER BONDING;

EID: 84866842263     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248898     Document Type: Conference Paper

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