Recent advances in flip-chip underfill: Materials, process, and reliability

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 3, 2004, Pages 515-524

  Zhang, Zhuqing ^a   Wong, C P ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CURING; ENCAPSULATION; EPOXY RESINS; PLASTICS FILLERS; RELIABILITY; SILICA; SOLDERED JOINTS; THERMAL EXPANSION; THERMAL STRESS;

FLIP CHIP INTERCONNECTION; FLIP CHIP UNDERFILL; MATERIAL DESIGN; MOLDED UNDERFILL; NO FLOW UNDERFILL; ORGANIC BOARD PACKAGE; WAFER LEVEL UNDERFILL;

FLIP CHIP DEVICES;

EID: 7244258739     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.831870     Document Type: Article

References (69)

1. C. P. Wong, S. Lou, and Z. Zhang, "Flip the chip," Science, vol. 290, p. 2269, Dec. 2000.
2. E. Davis, W. Harding, R. Schwartz, and J. Coring, "Solid logic technology: Versatile high performance microelectronics," in IBM J. Res. Develop., vol. 8, 1964, p. 102.
3. Y. Tsukada, "Surface laminar circuit and flip-chip attach packaging," in Proc. 42nd Electronic Components Technol. Conf., San Diego, CA, 1992, p. 22.
4. B. Han and Y. Guo, "Thermal deformation analysis of various electronic packaging products by moire and microscope moire interferometry," J. Electronic Packaging, vol. 117, p. 185, 1995.
5. W. M. Tsai, P. N. Houston, and D. F. Baldwin, "Flux-underfill compatibility and failure mode analysis in high yeild flip chip process," in Proc. IEEE/CPMT Int. Electronics Manufacturing Technology Symp., Santa Clara, CA, 2000, pp. 160-167.
6. S. Han, K. K. Wang, and S. Y. Cho, "Experimental and analytical study on the flow of encapsulant during underfill encapsulation of flip-chips," in Proc. 46th Electronic Components Technology Conf., Orlando, FL, 1996, pp. 327-334.
7. S. Han and K. K. Wang, "Pressurized Underfill Encapsulation of Integrated Circuits," U.S. Patent 6 000 924, Dec. 14, 1999.
8. S. Han, and K. K. Wang, "Study on the pressurized underfill encapsulation of flip chips," IEEE Trans. Comp., Packag., Manufact. Technol., B, vol. 20, pp. 434-442, Nov. 1999.
9. G. C. Kirkpatrick, M. Thavarajah, S. A. Patel, and S. A. Murphy, "Vacuum Assisted Underfill Process and Apparatus for Semiconductor Packaging Fabrication," U.S. Patent 5 998 242, Dec. 7, 1999.
10. S. Akram and J. M. Wark, "Method and Apparatus for Underfill of Bumped or Raised Die," U.S. Patent 6 066 509, May 23, 2000.
11. L. M. Higgins, J. C. Gentile, and S. C. Beddingfield, "Process for Underfilling a Flip-Chip Semiconductor Device," U.S. Patent 5 710 071, Jan. 20, 1998.
12. R. Pennisi and M. Papageorge, "Adhesive and Encapsulant Material with Fluxing Properties," U.S. Patent 5 128 746, July 7, 1992.
13. C. P. Wong and D. Baldwin, "No-Flow Underfill for Flip-Chip Packages," U.S. Patent Disclosure, Apr. 1996.
14. C. P. Wong and S. H. Shi, "No-Flow Underfill of Epoxy Resin, Anhydride, Fluxing Agent and Surfactant," U.S. Patent 6 180 696, Jan. 30, 2001.
15. C. P. Wong, S. H. Shi, and G. Jefferson, "High performance no flow underfills for low-cost flip-chip applications," in Proc. 47th Electronic Components Technology Conf., San Jose, CA, 1997, p. 850.
16. C. P. Wong, S. H. Shi, and G. Jefferson, "High performance no-flow underfills for flip-chip applications: Material characterization," IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 21, p. 450, Sept. 1998.
17. Z. Zhang, S. H. Shi, and C. P. Wong, "Development of no-flow under-fill materials for lead-free bumped flip-chip applications," IEEE Trans. Comp., Packag. Technol., vol. 24, pp. 59-66, Mar. 2001.
18. Z. Zhang and C. P. Wong, "Development of no-flow underfill for lead-free bumped flip-chip assemblies," in Proc. Electronics Packaging Technology Conf., Singapore, 2000, pp. 234-240.
19. Z. Zhang, and C. P. Wong, "Study and modeling of the curing behavior of no-flow underfill," in Proc. 8th Int. Symp. Exhibition Advanced Packaging Materials Processes, Properties, Interfaces, Stone Mountain, GA, 2002, pp. 194-200.
20. C. P. Wong, D. Baldwin, M. B. Vincent, B. Fennell, L. J. Wang, and S. H. Shi, "Characterization of a no-flow underfill encapsulant during the solder reflow process," in Proc. 48th Electronic Components Technology Conf., Seattle, WA, 1998, p. 1253.
21. P. Morganelli and B. Wheelock, "Viscosity of a no-flow underfill during reflow and its relationship to solder wetting," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 163-166.
22. R. W. Johnson, M. A. Capote, S. Chu, L. Zhou, and B. Gao, " Reflow-curable polymer fluxes for flip chip encapsulation," in Proc. Int. Conf Multichip Modules High Density Packaging, Denver, CO, 1998, pp. 41-46.
23. S. H. Shi and C. P. Wong, "Study of the fluxing agent effects on the properties of no-flow underfill materials for flip-chip applications," in Proc. 48th Electronic Components Technology Conf., Seattle, WA, 1998, p. 117.
24. S. H. Shi, D. Lu, and C. P. Wong, "Study on the relationship between the surface composition of copper pads and no-flow underfill fluxing capability," in Proc. 5th Int. Symp. Advanced Packaging Materials: Processes, Properties, Interfaces, Braselton, GA, 1999, p. 325.
25. S. H. Shi and C. P. Wong, "Study of the fluxing agent effects on the properties of no-flow underfill materials for flip-chip applications," IEEE Trans. Comp. Packag. Technol. A, vol. 22, p. 141, June 1999.
26. P. Palm, K. Puhakka, J. Maattanen, T. Heimonen, and A. Tuominen, "Applicability of no-flow fluxing encapsulants and flip chip technology in volume production," in Proc. 4th Int. Conf. Adhesive Joining Coating Technology Electronics Manufacturing, Helsinki, Finland, 2000, pp. 163-167.
27. K. Puhakka and J. K. Kivilahti, "High density flip chip interconnections produced with in-situ underfills and compatible solder coatings," in Proc. 3rd Int. Conf. Adhesives Joining Coating Technology Electronics Manufacturing, Binghamton, NY, 1998, pp. 96-100.
28. T. Wang, T. H. Chew, Y. X. Chew, and L. Foo, "Reliability studies of flip chip package with reflowable underfill," in Proc. Pan Pacific Microelectronic Symp., Kauai, HI, Feb. 2001, pp. 65-70.
29. Z. Zhang and C. P. Wong, "Assembly of lead-free bumped flip-chip with no-flow underfills," IEEE Trans. Electron. Packag. Manufact., vol. 25, pp. 113-119, Apr., 2002.
30. D. Miller and D. F. Baldwin, "Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process," in Proc. 7th Int. Symp. Advanced Packaging Materials: Processes, Properties, Interfaces, Braselton, GA, 2001, pp. 51-56.
31. R. Zhao, R. W. Johnson, G. Jones, E. Yaeger, M. Konarski, P. Krug, and L. Crane, "Processing of fluxing underfills for flip chip-on-laminate assembly," in IPC SMEMA Council APEX, Proc. APEX, San Diego, CA, 2002, pp. S18-1-1-S18-1-7.
32. T. Wang, C. Lum, J. Kee, T. H. Chew, P. Miao, L. Foo, and C. Lin, "Studies on a reflowable underfill for flip chip application," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 323-329.
33. D. Gamota and C. M. Melton, "The development of reflowable materials systems to integrate the reflow and underfill dispensing processes for DCA/FCOB assembly," IEEE Trans. Comp. Packag. Technol. C, vol. 20, p. 183, July 1997.
34. X. Dai, M. V. Brillhart, M. Roesch, and P. S. Ho, "Adhesion and toughening mechanisms at underfill interfaces for flip-chip-on-organic-substrate packaging," IEEE Trans. Comp. Packag. Technol., vol. 23, pp. 117-127, Mar. 2000.
35. B. S. Smith, R. Thorpe, and D. F. Baldwin, "A reliability and failure mode analysis of no flow underfill materials for low cost flip chip assembly," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 1719-1730.
36. K. S. Moon, L. Fan, and C. P. Wong, "Study on the effect of toughening of no-flow underfill on fillet cracking," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 167-173.
37. H. Wang and T. Tomaso, "Novel single pass reflow encapsulant for flip chip application," in Proc. 6th Int. Symp. Advanced Packaging Materials: Process, Properties, Interfaces, Braselton, GA, 2000, pp. 97-101.
38. Z. Zhang, L. Fan, and C. P. Wong, "Development of environmental friendly non-anhydride no-flow underfills," IEEE Trans. Comp. Packag. Technol., vol. 25, pp. 140-147, Mar. 2002.
39. S. H. Shi, Q. Yao, J. Qu, and C. P. Wong, "Study on the correlation of flip-chip reliability with mechanical properties of no-flow underfill materials," in Proc. 6th Int. Symp. Advanced Packaging Materials: Processes, Properties Interfaces, Braselton, GA, 2000, pp. 271-277.
40. S. H. Shi and C. P. Wong, "Recent advances in the development of no-flow underfill encapsulants - A practical approach towards the actual manufacturing application," in Proc. 49th Electronic Components Technology Conf., San Diego, CA, 1999, p. 770.
41. P. Miao, Y. Chew, T. Wang, and L. Foo, "Flip-chip assembly development via modified reflowable underfill process," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 174-180.
42. H. Noro, M. Mizutani, M. Kuwamura, H. Usui, and S. Ito, "Study of reliability and process ability for preset underfill sheet material as future standard flip chip packaging process," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 319-322.
43. Z. Zhang, J. Lu, and C. P. Wong, "A Novel Process Approach to Incorporate Silica Filler Into No-Flow Underfill," U.S. Provisional Patent 60/288 246, May 2, 2001.
44. Z. Zhang, J. Lu, and C. P. Wong, "A novel approach for incorporating silica fillers into no-flow underfill," in Proc. 51st Electronic Components Technology Conf, Orlando, FL, 2001, pp. 310-316.
45. Z. Zhang and C. P. Wong, "Novel filled no-flow underfill materials and process," in Proc. 8th Int. Symp. Exhibition Advanced Packaging Materials Processes, Properties Interfaces, Stone Mountain, GA, 2002, pp. 201-209.
46. K. M. Gross, S. Hackett, D. G. Larkey, M. J. Scheultz, and W. Thompson, "New materials for high performance no-flow underfill," in Symp. Proc. IMAPS, Denver, CO, Sept. 2002.
47. P. O. Weber, "Chip Package with Molded Underfill," U.S. Patent 6 038 136, Mar. 14, 2000.
48. P. O. Weber, "Chip Package with Transfer Mold Underfill," U.S. Patent 6 157 086, Dec. 5, 2000.
49. K. Gilleo, B. Cotterman, and T. Chen, "Molded underfill for flip chip in package," High Density Interconnection, p. 28, June 2000.
50. T. Braun, K. F. Becker, M. Koch, V. Bader, R. Aschenbrenner, and H. Reichl, "Flip chip molding - Recent progress in flip chip encapsulation," in Proc. 8th Int. Advanced Packaging Materials Symp., Stone Mountain, GA, Mar. 2002, pp. 151-159.
51. F. Liu, Y. P. Wang, K. Chai, and T. D. Her, "Characterization of molded underfill material for flip chip ball grid array packages," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 288-292.
52. L. P. Rector, S. Gong, T. R. Miles, and K. Gaffney, "Transfer molding encapsulation of flip chip array packages," in Proc. IMAPS, Boston, MA, 2000, pp. 760-766.
53. L. P. Rector, S. Gong, and K. Gaffney, "On the performance of epoxy molding compounds for flip chip transfer molding encapsulation," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 293-297.
54. K. F. Becker, T. Braun, M. Koch, F. Ansorge, R. Aschenbrenner, and H. Reichl, "Advanced flip chip encapsulation: Transfer molding process for simultaneous underfilling and postencapsulation," in Proc. 1st Int. IEEE Conf. Polymers Adhesives Microelectronics Photonics, Potsdam, Germany, 2001, pp. 130-139.
55. S. H. Shi, T. Yamashita, and C. P. Wong, "Development of the wafer-level compressive-flow underfill process and its required materials," in Proc. 49th Electronic Components Technology Conf., San Diego, CA, 1999, p. 961.
56. S. H. Shi, T. Yamashita, and C. P. Wong, "Development of the wafer-level compressive-flow underfill encapsulant," in Proc. 5th Int. Symp. Advanced Packaging Materials: Processes, Properties Interfaces, Braselton, GA, 1999, p. 337.
57. K. Gilleo and D. Blumel, "Transforming flip chip into CSP with reworkable wafer-level underfill," in Proc. Pan Pacific Microelectronics Symp., Kuauai, HI, 1999, p. 159.
58. K. Gilleo, "Flip Chip with Integrated Flux, Mask and Underfill," W.O. Patent 99/56312, Nov. 4, 1999.
59. J. Qi, P. Kulkarni, N. Yala, J. Danvir, M. Chason, R. W. Johnson, R. Zhao, L. Crane, M. Konarski, E. Yaeger, A. Torres, R. Tishkoff, and P. Krug, "Assembly of flip chips utilizing wafer applied underfill," in Proc. IPC SMEMA Council APEX, San Diego, CA, 2002, pp. S18-3-1-S18-3-7.
60. Q. Tong, B. Ma, E. Zhang, A. Savoca, L. Nguyen, C. Quentin, S. Lou, H. Li, L. Fan, and C. P. Wong, "Recent advances on a wafer-level flip chip packaging process," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 101-106.
61. S. Charles, M. Kropp, R. Kinney, S. Hackett, R. Zenner, F. B. Li, R. Mader, P. Hogerton, A. Chaudhuri, F. Stepniak, and M. Walsh, " Pre-applied underfill adhesives for flip chip attachment," in Proc. IMAPS Int. Symp. Microelectronics, Baltimore, MD, 2001, pp. 178-183.
62. B. Ma, Q. K. Tong, E. Zhang, S. H. Hong, and A. Savoca, "Materials challenges for wafer-level flip chip packaging," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 171-174.
63. C. D. Johnson and D. F. Baldwin, "Wafer scale packaging based on underfill applied at the wafer level for low-cost flip chip processing," in Proc. 49th Electronic Components Technology Conf., San Diego, CA, 1999, p. 951.
64. M. Chason, J. Danvir, N. Yala, J. Qi, P. Neathway, K. Tojima, W. Johnson, P. Kulkarni, L. Crane, M. Konarski, and E. Yaeger, "Development of wafer scale applied reworkable fluxing underfill for direct chip attach," in Proc. Assembly Process Exhibition Conf. 2001, San Diego, CA, 2001.
65. L. Crane, M. Konarski, E. Yaeger, A. Torres, R. Tishkoff, P. Krug, S. Bauman, W. Johnson, P. Kulkanari, R. Zhao, M. Chason, J. Danvir, N. Yala, and J. Qi, "Development of wafer scale applied reworkable fluxing underfill for direct chip attach, part II," in Proc. IPC SMEMA Council, San Diego, CA, 2002, pp. $36-2-1-$36-2-6.
66. L. Nguyen and H. Hguyen, "Solder joint shape formation under constrained boundaries in wafer-level underfill," in Proc. 50th Electronic Components Technology Conf., Las Vegas, NV, 2000, pp. 1320-1325.
67. J. Lu, S. C. Busch, and D. F. Baldwin, "Solder wetting in a wafer-level flip chip assembly," IEEE Trans. Electron. Packag. Manufact., vol. 24, pp. 154-159, 2001.
68. R. L. D. Zenner and B. S. Carpenter, "Wafer-applied underfill film laminating," in Proc. 8th Int. Symp. Advanced Packaging Materials, Stone Mountian, GA, 2002, pp. 317-325.
69. R. V. Burress, M. A. Capote, Y.-J. Lee, H. A. Lenos, and J. F. Zamora, "A practical, flip-chip multi-layer pre-encapsulation technology for wafer-scale underfill," in Proc. 51st Electronic Components Technology Conf., Orlando, FL, 2001, pp. 777-781.