System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 234-241

  Dong, Xiangyu ^a   Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3-D INTEGRATIONS; 3D IC DESIGNS; COST ANALYSIS; COST SAVINGS; COST-EFFECTIVE TECHNOLOGIES; DESIGN OPTIONS; DESIGN SPACE EXPLORATIONS; DESIGN STRATEGIES; EARLY DESIGN STAGES; ESTIMATION METHODS; HETEROGENEOUS INTEGRATIONS; IC DESIGNS; SYSTEM LEVELS; THREE-DIMENSIONAL INTEGRATED CIRCUITS;

COMPUTER AIDED DESIGN; COST ACCOUNTING; COST EFFECTIVENESS; COSTS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; SPACE RESEARCH; THREE DIMENSIONAL;

COST BENEFIT ANALYSIS;

EID: 64549095226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796486     Document Type: Conference Paper

References (25)

1. K. Bernstein, "New Dimension in Performance," EDA Forum,vol. 3, no. 2, 2006.
2. T. Vucurevich, "The Long Road to 3D Integration: Are We There Yet?" in Keynote speech at the 3D Architecture Conference, 2007.
3. W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, "Demystifying 3D ICs: the Pros and Cons of Going Vertical," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498-510, 2005.
4. G. H. Loh, Y. Xie, and B. Black, "Processor Design in 3D Die-Stacking Technologies," MICRO, 2007.
5. Y. Xie, G. H. Loh, B. Black, and K. Bernstein, "Design Space Exploration for 3D Architectures," J. Emerg. Technol. Comput. Syst.,vol.2, no. 2, pp. 65-103, 2006.
6. C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S. S. Sapatnekar, "Placement and Routing in 3D Integrated Circuits," IEEE Design and Test ofComputers, vol. 22, no. 6, pp. 520- 531, 2005.
7. X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," in Design Automation Conference, 2008, pp. 554-559.
8. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A Novel 3D Stacked MRAM Cache Architecture for CMPs," in International Symposium on High Performance Computer Architecture, 2009.
9. J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," in International Conference on Computer Aided Design, 2004, pp. 306-313.
10. S. Das, A. Chandrakasan, and R. Reif, "Design Tools for 3-D Integrated Circuits," in ASPDAC, 2003, pp. 53-56.
11. Y. Deng and W. Maly, "A Feasibility Study of 2.5D System Integration," in Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, 2003, pp. 667-670.
12. L. Smith, G. Smith, S. Hosali, and S. Arkalgud, "3D: It All Comes Down to Cost," Proceedings ofRTIConference of3D Architecture for Semiconductors and Packaging, 2007.
13. B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship For Partitions of Logic Graphs," IEEE Trans. on Computers, vol. C-20, no. 12, pp. 1469-1479, 1971.
14. W. E. Donath, "Placement and Average Interconnection Lengths of Computer Logic," IEEE Trans. on Circuits and Systems, vol. 26, no. 4, pp. 272-277, 1979.
15. J. A. Davis, V. K. De, and J. D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)IPart I: Derivation and Validation," IEEE Trans. on Electron Devices, vol. 45, no. 3, pp. 580-589, 1998.
16. R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs," in ICCAD, 2007, pp. 212-219.
17. A. B. Kahng, S. Mantik, and D. Stroobandt, "Toward Accurate Models of Achievable Routing," IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, vol. 20, no. 5, pp. 648-659, 2001.
18. P. Chong and R. K. Brayton, "Estimating and Optimizing Routing Utilization in DSM Design," in Workshop System-Level Interconnect Prediction, 1999.
19. S. C. Marc Tremblay, "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor," in International Solid State Circuit Conference, 2008, pp. 82-83.
20. J. Rabaey, A. Chandrakasan, and B. Nikolic, "Digital Integrated Circuits," Prentice-Hall, 2003.
21. "IC Cost Model, 2008 revision 0808a," in IC Knowledge LLC, 2008.
22. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
23. S. Borkar, "3D-Technology: A System Perspective," in International 3D- System Integration Conference, 2008.
24. "http://techresearch.intel.com/articles/Tera-Scale/1421.htm," 2007.
25. "http://www.opensparc.net/," 2008.