Study on hybrid au-underfill resin bonding method with lock-and-key structure for 3-D integration

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 3, Issue 4, 2013, Pages 558-565

  Nimura, Masatsugu ^a   Mizuno, Jun ^a   Shigetou, Akitsu ^b   Sakuma, Katsuyuki ^c   Ogino, Hiroshi ^d   Enomoto, Tomoyuki ^d   Shoji, Shuichi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE FOR MATERIALS SCIENCE   (Japan)

^c IBM MICROELECTRONICS   (United States)

^d NISSAN CHEMICAL INDUSTRIES LTD   (Japan)

Author keywords

3 D integration; Au bump; bonding; flip chip; micro bump; underfill

Indexed keywords

3-D INTEGRATION; AU BUMP; FLIP CHIP; MICRO-BUMPS; UNDERFILLS;

BONDING; GOLD; INTEGRATION; PHOTOLITHOGRAPHY; RESINS; TRANSMISSION ELECTRON MICROSCOPY;

KEYS (FOR LOCKS);

EID: 84875907152     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2013.2240566     Document Type: Article

References (11)

1. M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp. 17-21, Jul.-Aug. 1998. (Pubitemid 128576212)
2. K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbrocker, "3-D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections," Int. Bus. Mach. J. Res. Develop., vol. 52, no. 6, pp. 611-622, Nov. 2008.
3. S. Han and K. K. Wang, "Analysis of the flow of encapsulant during underfill encapsulation of flip-chips," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 20, no. 4, pp. 424-591, Nov. 1997.
4. K. Sakuma, S. Kohara, K. Sueoka, Y. Orii, M. Kawakami, K. Asai, Y. Hirayama, and J. U. Knickerbrocker, "Development of vacuum underfill technology for a 3-D chip stack," J. Micromech. Microeng., vol. 21, no. 3, p. 035024, Feb. 2011.
5. S. Kawamoto, O. Suzuki, and Y. Abe, "The effect of filler on the solder connection for no-flow underfill," in Proc. 51th Electron. Compon. Technol. Conf., May-Jun. 2006, pp. 479-484. (Pubitemid 44929720)
6. J.-W. Nah, M. A. Gaynes, and C. Feger, "Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging," in Proc. 63th Electron. Compon. Technol. Conf., May-Jun. 2011, pp. 1015-1022.
7. A. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, and T. Suga, "Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding method," IEEE Trans. Adv. Packag., vol. 29, no. 2, pp. 218-226, May 2006.
8. J. J. McMahon, E. Chan, S. H. Lee, R. J. Gutmann, and J.-Q. Lu, "Bonding interfaces in wafer-level metal/adhesive bonded 3D integration," in Proc. 58th Electron. Compon. Technol. Conf., May 2008, pp. 871-878.
9. T. Sakai, S. Seiki, and M. Mizukoshi, "A new flip chip bonding method using ultra-precision cutting of metal/adhesive layers, " in Proc. Int. Conf. Electron. Packag., Apr. 2007, pp. 99-104.
10. F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K.-N. Chen, X. Li, D. A. Dipaola, D. Brown, C. T. Ryan, J. A. Hagan, K. H. Wong, M. Lu, X. Gu, N. R. Klymko, E. D. Perfecto, A. G. Merryman, K. A. Kelly, S. Purushothaman, S. J. Koester, R. Wisnieff, and W. Haensch, "A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding," in Int. Electron Devices Meeting Tech. Dig., Dec. 2008, pp. 1-4.
11. M. Nimura, A. Shigetou, K. Sakuma, H. Ogino, T. Enomoto, J. Mizuno, and S. Shoji, "Hybrid Au-underfill resin bonding with lockand-key structure," in Proc. 62nd Electron. Compon. Technol. Conf., May-Jun. 2012, pp. 258-262.