3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 795-801

  Lee, S W Ricky ^a   Hon, Ronald ^a   Zhang, Shawn X D ^a   Wong, C K ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVES; ETCHING; FILLING; FLIP CHIP DEVICES; MICROELECTRONICS; SILICON;

ADHESIVE DISPENSING; ION ETCHING; SYSTEM ON CHIP;

MICROPROCESSOR CHIPS;

EID: 24644433947     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Reichl, H., Ostmann, A., Wieland, R. and Ramm, P., "The Third Dimension in Microelectronics Packaging,", Proc. 14th European Microelectronics & Packaging Conference and Exhibition, Friedrichshafen, Germany, June 23-25, 2003.
2. Spiesshoefer, S., Schaper, L., Burkett, S., Vangara, G., Rahman, Z. and Arunasalam, P., "Z-Axis Interconnects Using Fine Pitch, Nanoscale Through Silicon Vias: Process Development," Proc. 54th Electronic Components & Technology Conference, Las Vegas, NV, June 1-4, 2004, pp. 466-471.
3. Spiesshoefer, S. and Schaper, L., "IC Stacking Technology Using Fine Pitch, Nanoscale Through Silicon Vias," Proc. 53rd Electronic Components & Technology Conference, New Orleans, LA, May 27-30, 2003, pp. 631-633.
4. Lee, R. A. and Whittaker, D. R., "Laser Created Silicon Vias For Stacking Dies in MCMs," Proc. Electronics Manufacturing Technology Symposium, 1991, pp. 262-265.
5. Sun, Y. and Swenson, E., "Lasers in Electronics Packaging," Proc. 5th International Conference on Electronic Packaging Technology, October 28-30, 2003, pp. 167-170.
6. Wang, L., Nichelatti, A., Schellevis, H., de Boer, C., Visser, C., Nguyen, T. N. and Sarro, P. M., "High Aspect Ratio Through-Wafer Interconnections for 3D-Microsystems," Proc. 16th IEEE International Conference on MEMS, Kyoto, Japan, January 19-23, 2003, pp. 634-637.
7. Yeom, J., Wu, Y. and Shannon, M. A., "Critical Aspect Ratio Dependence in Deep Reactive Ion Etching of Silicon," Proc. 12th International Conference on Transducers, Solid-State Sensors, Actuators & Microsystems, June 8-12, 2003, pp. 1631-1634.
8. Takahashi, K., Taguchi, Y., Tomisaka, M. and Yonemura, H. et al, "Process Integration of 3D Chip Stack with Vertical Interconnection," Proc. 54th Electronic Components & Technology Conference, Las Vegas, NV, June 1-4, 2004, pp. 601-609.
9. Umemoto, M., Tanida, K., Nemoto, Y., Hoshino, M., Kojima, K., Shirai Y. and Takahashi, K., "High-Performance Vertical Interconnection for High-Density 3D Chip Stacking Package," Proc. 54th Electronic Components & Technology Conference, Las Vegas, NV, June 1-4, 2004, pp. 616-623.
10. Nguyen, N. T., Boellaard, E. and Pham, N. P., Kutchoukov, V. G., Craciun, G. and Sarro, P. M., "Through-wafer Copper Electroplating for Three-dimensional Interconnects," Journal of Micromechanics and Microengineering, 2002 (12), pp. 395-399.