3D chip stacking with C4 technology

IBM Journal of Research and Development

Volumn 52, Issue 6, 2008, Pages 599-609

  Dang, Bing ^a   Wright, Steven L ^a   Andry, Paul S ^a   Sprogis, Edmund J ^b   Tsang, Cornelia K ^a   Interrante, Mario J ^c   Webb, Bucknell C ^a   Polastre, Robert J ^a   Horton, Raymond R ^a   Patel, Chirag S ^a   Sharma, Arun ^a   Zheng, Jiantao ^c   Sakuma, Katsuyuki ^d   Knickerbocker, John U ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

^c IBM MICROELECTRONICS   (United States)

^d IBM RESEARCH TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP CHIP DEVICES; LOW POWER ELECTRONICS;

CHIP ATTACHMENT; CHIP PLACEMENT; HIGH BANDWIDTH; REFLOW PROCESS; SMALL FORM FACTORS; STACKING SCHEME; THREE DIMENSIONAL (3D) INTEGRATION; VARIOUS SUBSTRATES;

CHIP SCALE PACKAGES;

EID: 61649084986     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2008.5388560     Document Type: Article

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