Wafer-level bonding/stacking technology for 3D integration

Microelectronics Reliability

Volumn 50, Issue 4, 2010, Pages 481-488

  Ko, Cheng Ta ^a   Chen, Kuan Neng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BONDING CONDITIONS; BONDING MATERIALS; BONDING TECHNOLOGY; ENHANCED TRANSMISSION; FORM FACTORS; LOWER-POWER CONSUMPTION; WAFER LEVEL;

APPROXIMATION THEORY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 77950021566     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.09.015     Document Type: Article

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