3D copper TSV integration, testing and reliability

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Farooq, M G ^a   Graves Abe, T L ^a   Landers, W F ^a   Kothandaraman, C ^a   Himmel, B A ^a   Andry, P S ^a   Tsang, C K ^a   Sprogis, E ^a   Volant, R P ^a   Petrarca, K S ^a   Winstel, K R ^a   Safran, J M ^a   Sullivan, T D ^a   Chen, F ^a   Shapiro, M J ^a   Hannon, R ^a   Liptak, R ^a   Berger, D ^a   Iyer, S S ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEOL STRUCTURES; EMBEDDED DRAM; FUNCTIONAL DATAS; SIGNIFICANT IMPACTS;

ELECTRON DEVICES;

THREE DIMENSIONAL;

EID: 84856981864     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131504     Document Type: Conference Paper

References (11)

1. S.S. Iyer, T. Kirihata, M.R. Wordeman, J. Barth, R.H. Hannon & R. Malik, "Process-design considerations for three dimensional memory integration, " VLSI Tech Symp p 60, 2009.
2. Special Issue of the IBM Journal. of Res and Dev 52 (6), 2008.
3. M.G. Farooq, ECS Transactions 35 (2) p 83, 2011.
4. J. Golz et al, "3D stackable 32nm high-K/metal gate SOI embedded DRAM prototype," Symp on VLSI Circuits, Kyoto, June 2011.
5. P.S. Andry, et al. "A CMOS-compatible process for fabricating electrical through-vias in silicon," Proc of the 56th ECTC p 831, 2006.
6. A. Mercha et al, "Impact of thinning and TSV proximity on high-k/metal gate first CMOS performance," Proc of the IEEE VLSI Technology Conference p 109, 2010.
7. N. Khan S. M. Alam, S. Hassoun, "TSV-induced noise characterization and noise mitigation using coaxial TSVs," Proc of the IEEE ECTC, 2009.
8. Y. Yang, G. Katti, R. Labie, Y. Travaly, B. Verlinden, and I. De Wolf, "Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure," Proc of the IEEE IITC (9.4), 2010.
9. J. Barth et al, "A 45 nm SOI embedded DRAM Macro for the POWER processor 32MByte on-chip L3 cache," IEEE Journal of Solid State Circuits 46 (1) p 64, 2011.
10. M. Jacunski et al, "A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns," CICC Dig Tech papers 2010.
11. N. Butt et al, "A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology," Tech Dig IEDM p 27.5.1, 2010.