Assembly and reliability characterization of 3D chip stacking with 30μm pitch lead-free solder micro bump interconnection

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1043-1049

  Zhan, Chau Jie ^a   Chuang, Chun Chih ^a   Juang, Jing Ye ^a   Lu, Su Tsai ^a   Chang, Tao Chih ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; 3D-CHIP STACKING TECHNOLOGY; CHIP STACKING; CHIP-ON-CHIP; CRITICAL ISSUES; CURRENT-STRESSING; ELECTRICAL EVALUATIONS; ELECTRONIC DEVICE; ELECTRONIC PACKAGING; FINE PITCH; GAP FILLING; HIGH CURRENTS; HIGH DENSITY; INPUT/OUTPUT; JOINT RELIABILITY; LEAD FREE SOLDERS; LEAD-FREE; MICRO-BUMPS; MICRO-ELECTRONIC DEVICES; MICROSTRUCTURE EVOLUTIONS; MULTI-FUNCTIONS; RELIABILITY CHARACTERIZATION; RELIABILITY TEST; SN-AG SOLDER; SOLDER BUMP; SOLDER MATERIAL; TEMPERATURE CYCLING TESTS; TEST VEHICLE; TWO LAYERS; UNDER-BUMP METALLURGIES; UNDERFILL DISPENSING; UNDERFILLS;

ELECTROMIGRATION; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; LEAD; MICROELECTRONICS; RELIABILITY; SILVER; SOLDERING; TECHNOLOGY; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 77955212633     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490829     Document Type: Conference Paper

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