ONO Structures and Oxynitrides in Modern Microelectronics: Material Science, Characterization and Application

Dielectric Films for Advanced Microelectronics

Volumn , Issue , 2007, Pages 251-295

  Roizin, Yakov ^a   Gritsenko, Vladimir ^b  

^a TOWER SEMICONDUCTOR LTD   (Israel)

^b INSTITUTE OF SEMICONDUCTOR PHYSICS   (Russian Federation)

Author keywords

Electron energy loss spectroscopy (EELS); Metal nitride oxide semiconductor (MNOS); Nitride layer ONO traps; Nitride oxynitride films and ONO stacks; ONO structures and oxynitrides; Random mixture model (RMM) and random bonding model (RBM); Silicon oxynitride atomic structure; Stacked ON or ONO (oxide nitride oxide) structures

Indexed keywords

CRYSTAL ATOMIC STRUCTURE; ELECTRON ENERGY LEVELS; ELECTRON ENERGY LOSS SPECTROSCOPY; ELECTRON SCATTERING; ENERGY DISSIPATION; MICROELECTRONICS; NITRIDES; OXIDE FILMS; OXIDE SEMICONDUCTORS; REFRACTORY METAL COMPOUNDS;

METAL NITRIDES; NITRIDE LAYERS; OXIDE NITRIDE OXIDES; OXYNITRIDES; RANDOM BONDING MODEL; SILICON OXYNITRIDES;

SILICON COMPOUNDS;

EID: 84950314534     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9780470017944.ch6     Document Type: Chapter

References (109)

1. M. Specht, U. Dorda, L. Dreeskornfeld, J. Kretz, F. Hofmann, M. Städele, R.J. Luyken, W. Rösner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, R. Kommling, and L. Risch, 20 nm tri-gate SONOS memory cells with multi-level operation, IEDM Technical. Digest, 1083-1086 (2004).
2. B. Eitan, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping, US Patent 5,768,192, 1998.
3. 2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits, J. Appl. Phys., 90, 2057-2122 (2001).
4. E.P. Gusev, H-C. Lu, E.L. Garfunkel, T. Gustafsson, and M.L. Green, Growth and characterization of ultrathin nitrided silicon oxide films, IBM Journal of Reasearch and Development, 43, 265-285 (1999).
5. I. Levin, M. Kovler, Y. Roizin, M. Vofsi, R.D. Leapman, G. Goodman, N. Kawada, and M. Funahashi, Structure, chemistry, and electrical performance of silicon oxide-nitride-oxide stacks on silicon, Journal of The Electrochemical Society, 151, G833-G838 (2004).
6. M.H. White, D.A. Adams, J.R. Murray, S. Wrazien, Y. Zhao, Yu. Wang, Khan, W. Miller, and R. Mehrotra, Characterization of scaled SONOS EEPROM, Memory Devices for Space and Military Systems, Non-Volatile Memory Technology Symposium, 51-59, 15 Nov. 2004.
7. T.P. Ma, Making silicon nitride fi lm a viable gate dielectric, IEEE Transact., ED-45, 680-690 (1998).
8. H. Goto, K. Shibahara, and S. Yokoyama, Atomic layer controlled deposition of silicon nitride with self-limiting mechanism, Applied Physics Letters, 68(23), 3257-3259 (1996).
9. M. She, H. Takeuchi, and T.-J. KIng, Silicon-nitride as a tunnel dielectric for improved SONOS type fl ash memory, IEEE ED Letters, 24, 309-311 (2003).
10. H.Y.A. Chung, J. Niess, W. Dietl, G. Roters, W. Lerch, Z. Nenyei, A. Ludsteck, J. Schulze, I. Eisele, K. Wieczorek, and N. Krumm, RTP-Grown Oxynitride Layers Meet Gate Challenges, Semiconductor International, September 2001 (2004).
11. S. Wolf and R.N. Taubner, Silicon processing for the VLSI Era, Vol.1, Lattice press, Sunset Beach, CA, 2000.
12. D. Dobkin, Thermal CVD of silicon nitride; Plasma-enhanced CVD of silicon nitride. http:// www.enigmatic-consulting.com/semiconductor_processing.
13. V.J. Kapoor, R.S. Bailey, and H.J. Stein, Hydrogen and silicon related memory traps in thin silicon nitride films, Journal of Vacuum Science and Technology, A1(2), 600 (1983).
14. A. Nakajima, T. Yoshimoto, T. Kidera, and S. Yokoyama, Low temperaqture formation of silicon nitride gate dielectrics by atomic layer deposition, Applied Physics Letters, 79, 665-667 (2001).
15. W-T. Li, D.R. McKenzie, W.D. McFall, and Qi-Chu Zhang, Effect of sputtering gas pressure on properties of silicon nitride fi lms produced by helicon plasma sputtering, Thin Solid films, 384, 46-52 (2001).
16. S.V. Hattangady, G.G. Fountain, R.A. Rudder, and R.J. Markunas, Low hydrogen content silicon nitride deposited at low temperature, J. Vac. Sci. and Tech., A7, 570-575 (1998).
17. Peter Singer, Dual Liner Stresses NMOS and PMOS, Semiconductor International, 1/1 (2005).
18. J. Caughman, D. Beach, J. Jellison, W. Wardner, and H. Bola George, Dielectric properties of silicon nitride deposited by high density plasma enhanced chemical vapor deposition, 46th AVS National Symposium, October 25, 1999.
19. H.Y. Yu, Y.T. Hou, M.F. Li, and D.L. Kwong, Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-MOSFET. IEEE ED Letters, 23, 285-287 (2002).
20. 2/Si interface on reliability issues-negative-bias-temperature instability and Fowler-Nordheim-stress degradation, Applied Physics Letters, 81, 4362-4364 (2002).
21. T. Sasaki, K. Kuwazawa, K. Tanaka, J. Kato, and D.L. Kwong, Engineering of nitrogen profile in ultrathin gate insulator to improve transistor performance and NBTI, IEEE ED Letters, 24, 150-152 (2003).
22. E. Cartier, D.A. Buchanan, and G.J. Dunn, Atomic hydrogen-induced interface degradation of reoxidized-nitrided silicon dioxide on silicon, Appl. Phys. Lett., 64, 901 (1994).
23. D.H. Schroder and J.A. Babcock, NBTI-Road to cross in deep submicron semiconductor manufacturing, J. Appl. Phys., 94(1), 1-18 (2003).
24. S.P. Tay and Y.Z. Hu, UV enhanced Si oxynitridation, SEMICON China SEMI Technology Symposium, 2004.
25. M. Lisiansky, A. Heiman, G. Garteiz, E. Alon, A. Fenigstein, Y. Roizin, A. Gladkikh, M. Oksman, R. Edrei, A. Hoffman, G. Xing, and G. Cautiero, ISSG-SiNGen ONO stack for NROM memory: Electrical and Chemical Characterization. ECS 2005 Meeting, Montreal, Canada, 2005.
26. I. Levin, R.D. Leapman, M. Kovler, and Y. Roizin, Radiation-induced nitrogen segregation during electron energy loss spectroscopy of silicon oxide-nitride-oxide stacks, Applied Physics Letters, 83, 1548-1550 (2003).
27. 3. Surface and Interface Analyses, 34, 456-459 (2002).
28. A. Karamcheti, V.H.C. Watt, H.N. Al-Shareef, T.Y. Luo, G.A. Brown, M.D. Jackson, and H.R. Huff, Silicon oxynitride fi lms as a segue to the high-K era, Semiconductor Fabtech, 12, 27-214 (2000).
29. 2 films, J. Appl. Phys., 91(1), 48-55 (2002).
30. G. Lucovsky, Ultrathin nitrided gate dielectrics: Plasma processing, chemical characterization, performance and reliability, IBM J. Research Develop., 43, 301-326 (1999).
31. V.S. Chang, C.C. Chen, Y. Lin, C.H. Chen, T.L. Lee, S.C. Chen, and M.S. Liang, Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitide/oxide stack model, 2004 IEEE ICICDT, Austin, TX, 363-366 (2004).
32. Q. Lu, Y.C. Yeo, K.J. Yang, R. Lin, I. Polishchuk, T.J. King, C. Hu, S.C. Song, H.F. Luan, D.L. Kwong, X. Guo, Z. Luo, X. Wang, and T.P. Ma, Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric, IEEE Electron Device Letters, 22, 324-326 (2001).
33. M. She, T.J. King, C. Hu, W. Zhu, Z. Luo, J.P. Han, and T.P. Ma, JVD silicon nitride as tunnel dielectric in p-channel flash memory, IEEE ED Letters, 23, 91-93 (2002).
34. 3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability, Applied Physics Letters, 80, 1252-1254 (2002).
35. C.C. Finstad and A.J. Muscat, Atomic layer deposition of silicon nitride barrier layer for selfaligned gate stack, ECS National Meeting, Orlando, FL, October 2003.
36. I. Fujiwara, H. Aozasa, A. Nakamura, Y. Komatsu, and Y. Hayashi, 0.13 um MONOS single transistor memory cell with separated source lines, Jpn. J. Appl. Phys., 39, 417-423 (2000).
37. Y. Yang, A. Purwar, and M. White, Reliability considerations in scaled SONOS nonvolatile memory devices, Sol. St. Electronics, 43, 2025-2032 (1999).
38. Y. Roizin, Shternfeld-Lavie, and I. Edrei, SONOS embedded memory with CVD dielectric US Patent Application 20050186741, 2005.
39. B. de Salvo, C. Geraldi, R. Van Schajik, S. Lombardo, D. Corso, C. Plantamura, S. Serafino, G. Amemdola, M. van Duuren, P. Goarin, W.Y. Mei, K. van der Jeu, T. Baron, M. Gely, P. Mur, and S. Deleonibus, Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS), IEEE Transactions on Device and Materials reliability, 4, 377-389 (2004).
40. M. Tanaka, S. Saida, Y. Mitani, I. Mizushima, and Y. Tsunashima, Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps, in IEDM Tech. Dig, 237-240 (2002).
41. Y. Roizin, O. Gluzman, V. Kairys, and G. Shnaiderr, ONO engineering, Tower Semiconductor Internal Report, 2000.
42. Y. Roizin and B. Eitan, Oxide-nitide-oxide structure, US Patent Application 20030134476, 2003.
43. ADAMANT Consortium Public Report, WP3: Memory cells. 28 May 2004
44. T.S. Chen, K.H. Wu, and C.H. Kao, Performance improvement of SONOS memory by bandgap engineering of charge trapping layer, IEEE ED Letters, 25, 205-207 (2004).
45. T. Bohm, A. Nakamura, H. Aozasa, M. Yamacgishi, and Y. Komatsu, Development of subquarter MONOS type memory transistor, Jap. J. Appl. Phys., 35, 898-901 (1996).
46. 4 films, Solid State Electronics, 48, 477-482 (2004).
47. M. Naich, Rosenman and Ya. Roizin, Profiling of deep traps in silicon oxide-nitride-oxide structures, Thin Solid Films, 471, 166-169 (2005).
48. 2 interface using EELS and ellipsometric measurements, J. Electrochem. Soc., 146, 780-785 (1999).
49. y, Sov. Phys. JETP, 62, 321-327 (1985).
50. V.A. Gritsenko, H. Wong, J.B. Xu, R.M. Kwok, I.P. Petrenko, B.A. Zaitsev, Yu. N. Morokov, and Yu. N. Novikov, Comparative study of excess sSilicon at the silicon nitride /thermal oxide interface in oxide-nitride-oxide structures using SIMS, AES, and EELS, J. Appl. Phys., 86, 3234-3240 (1999).
51. 2 stacks obtained by thermal oxidation of silicon nitride layers, J. Vac. SciTech., 23 (2005).
52. G. Rosenman, M. Naich, Y. Roizin, and R. van Shajk, Deep traps in ONO stacks fabricated from hydrogen and deuterium containing precursors, J. Appl. Phy., 99, 023702-1-023702-4 (2006).
53. B. Kim, J.Y. Kim, and K.Y. Seo, A new charge-trapping nonvolatile memory based on the reoxidized nitrous oxide, Microelectronic Engineering, 77, 21-26 (2005).
54. T.C. Chang, S.T. Yan, P.T. Liu, C.W. Chen, Y.C. Wu, and S.M. Sze, Study on SONOS nonvolatile memory technology using high density plasma CVD silicon nitride, Electrochemical and Solid State Letters, 7G113-G115 (2004).
55. V.A. Gritsenko, J.B. Xu, I.H. Wilson, R.M. Kwok, and Y.H. Ng, Short range order and nature of defects and traps in amorphous silicon oxynitride, Phys. Rev. Lett., 81, 1054-1057 (1998).
56. x alloys in terms of a charge-transfer model, Phys. Rev., B 46, 12478-12484 (1992).
57. V.A. Gritsenko, R.W.M. Kwok, H. Wong, and J.B. Xu, Short-range order in non-stoichiometric amorphous silicon oxynitride and silicon-rich nitride, J. Non-Crystalline Solids, 297, 96-101 (2002).
58. V.A. Gritsenko, Yu. G. Shavalgin, P.A. Pundur, H. Wong, and W.M. Kwok, Short-range order and luminescence in amorphous silicon oxynitride, Philosopical Magazine, 80, 1857-1868 (2000).
59. V.A. Gritsenko, Structure and electronic properties of amorphous dielectrics in silicon MIS structures, Science, Novosibirsk, Russia, 1993.
60. V.A. Gritsenko, Electronic structure and optical properties of silicon nitride, in Silicon Nitride in Electronics, Elsevier, New York, 1988.
61. S.I. Raider, R. Flitsh, J.A. Aboa, and W.A. Pliskin, Surface oxidation of silicon nitride films, J. Electrochem Sos., 123, 560-565 (1976).
62. V.A. Gritsenko, E.E. Meerson, I.V. Travkov, and Yu. V. Goltvjanskii, Nonstationary electron and hole transport by depolarization of MNOS Structures: Experiment and numerical simulation, Microelectronics, 16, 42-50 (1987).
63. K.A. Nasyrov, V.A. Gritsenko, Yu. N. Novikov, E.-H. Lee, S.Y. Yoon, and C.W. Kim, Twobands charge transport in silicon nitride due to phonon-assisted trap ionization, J. Appl. Phys., 96, 4293-4296 (2004).
64. W.L. Warren, J. Robertson, E.H. Poindexter, and P.J. Mcwhorter, Electron paramagnetic resonance investigation of charge trapping centers in amorphous silicon nitride films, J. Appl. Phys., 74, 4034-4046 (1993).
65. P. Lenahan and J. Kanicki, Nature of the dominant deep trap in amorphous silicon nitride, Phys. Rev., B 38, 8226-8229 (1988).
66. 4, Phys. Rev., B 61, 15005-15009 (2000).
67. V.A. Gritsenko, Yu. N. Novikov, A.V. Shaposhnikov, H. Wong, and G.M. Zhidomirov, Capturing properties of a threefold coordinated silicon atom in silicon nitride: Positive correlation energy model, Physics of the Solid State, 45, 2031-2035 (2003).
68. 4, Semiconductors, 35, 997-1005 (2001).
69. 2, Microelectronics and Reliability, 38, 1457-1464 (1998).
70. V.A. Gritsenko and A.D. Milov, Wigner crystallization of electrons and holes in amorphous silicon nitride. Antiferromagnetic ordering of localized electron and holes as a result of a resonance exchange Interaction, Letters to Journal of Experimental and Theoretical Physics, 64, 531-537 (1996).
71. x: H films, Journal of Non-Crystalline Solids, 137&138, 61-64 (1991).
72. R. Prasad, Ground state structures and properties of small hydrogenated silicon Clusters, Bull. Mater. Sci., 26, 117-121 (2003).
73. M.J. Powell, R.B. Wehrspohn, and S.C. Deane, Nature of metastable and stable dangling bond defects in hydrogenated amorphous silicon, Journal of Non-Crystalline Solids, 299-302, 556-560 (2002).
74. A. Kolodziej, Staebler-Wronsky effect in amorphpous silicon and its alloys, Opto-Electronics Review, 12(1), 21-32 (2004).
75. Y. Roizin, L. Tsybeskov, and V. Shumeiko, Dynamic conductivity of amorphous silicon nitride, Sov. Phys. Solid State, 32, 167-168 (1990).
76. J.I. Frenkel, About electrical breakdown of dielectrics and semoconductor, Journal of Experimental and Theoretical Physics, 8, 1292-1301 (1938).
77. S.D. Ganichev, E. Ziemann, and W. Prettl, Distinction between the Poole-Frenkel and tunneling models of electric-field-stimulated carrier emission from deep levels in semiconductors, Phys. Rev., B 61, 10361-10365 (2000).
78. S. Makram-Ebeid and M. Lannoo, Quantum model for phonon-assisted tunnel ionization of deep levels in a semiconductors, Phys. Rev., B 25, 6406-6424 (1982).
79. V.N. Abakumov, V.I. Perel, and I.N. Yassievich, Nonradiative recombination in semiconductors, edited by V.M. Agranovich and A.A. Maradudin, Modern Problems in Condensed Matter Sciences Vol. 33, Amsterdam, 1991.
80. 4 interface and energy band diagram of metal-nitride-oxide-semiconductor structures, Phys. Rev., B 57, R2081-R2083 (1997).
81. Y. Roizin, V. Vasilenko, and L. Daus, Investigation of thin insulating films using the surface ionic charge technique, Thin Solid Films, 207, 185-192 (1992).
82. Y. Roizin, A. Yankelevich, and Y. Netzer, Novel techniques for data retention and Leff measurements in two bit microFLASH® memory cells, AIP Conf. Proc., 550, 181-184 (2001).
83. Y. Roizin, E. Aloni, M. Gutman, V. Kairys, and P. Zisman, Retention characteristics of micro- FLASH® Memory, IEEE 2001 NVSMW, Monterey, CA, 128-129, 2001.
84. Y. Roizin, R. Daniel, S. Greenberg, M. Gutman, M. Lisiansky, V. Kairys, and P. Zisman, Interface traps and reliability performance of microFlash® memory. IEEE NVM Workshop, Monterey, 85-87, 2004.
85. H. Wegener, A. Lincoln, H. Pao, M. O'Connell, and R. Oleksiak, The variable threshold transistor, a new electrically-altyerable, non-destructive read-only storage device. IEEE IEDM Techn. Dig., Washington, DC, 1967.
86. S.K. Sung, I.H. Park, C.J. Lee, Y.K. Lee, J.D. Lee, B-G. Park, S.D. Chae, and C.W. Kim, Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices, IEEE Trans. on Nanotechnology, 2, 258-264 (2003).
87. R. van Schaijk, M. van Duuren, P. Goarin, M. Slotboom, Wan Yuet Mei 1, and K. van der Jeugd, Reliability of embedded SONOS memories, ESSDERC 2004, Leuven, Belgium, 277-280, 2004.
88. J. Bu and M.H. White, Design considerations in scaled SONOS nonvolatile memory devices, Solid State Electronics, 45, 113-117 (2001).
89. S. Chae, C. Lee, J. Kim, S. Sung, J. Sim, M. Kim, S. Yoon, Y. Jeong, W. Ryu, T. Kim, D-G. Park, J.-W. Lee, and C.W. Kim, 70 nm SONOS Nonvolatile memory devices using Fowler- Nordheim programming and hot hole erase method, Jap. Journal Appl. Phys., 43, 2207-2210 (2004).
90. Y. Kamigaki and S. Minami, MNOS nonvolatile semiconductor memory technology: Present and future. IEICE Trans. Electron, E84-C, 713-723 (2001).
91. I.H. Cho, B.G. Park, J.D. Lee, and J.H. Lee, Nano-Scale SONOS memory with a Double-Gate MOSFET Structure, J. Korean Phys. Soc., 42, 233-236 (2003).
92. P. Singer, FinFET used in smallest Non-Volatile memory, Semiconductor International, 2/1 (2005).
93. M.K. Kim, S.D. Chae, H.S. Chae, J.H. Kim, Y.S. Jeong, H. Silva, and S. Tiwari, Ultra-short SONOS memories, IEEE Transactions on Nanotechnology, 3(4), 417-424 (2004).
94. E. Lusky, Y. Shacham-Diamand, G. Mitenberg, A. Shappir, I. Bloom, and B. Eitan, Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices, IEEE Transactions, ED-51, 444-451 (2004).
95. B. Eitan, Reducing secondary injection effects, US Patent 6,583,007, 2003.
96. D. Fuks, A. Kiv, T. Maximova, R. Bibi, Y. Roizin, and M. Gutman, Computer modeling of the trapping media in microFlash memory devices, J. Computer Aided Material Design, 9, 21-32 (2002).
97. Y. Roizin, M. Gutman, S. Alfassi, and R. Yosefi , In process charging in microFlash memory cells, IEEE NVM Workshop, Monterey, CA, 83-84, 2003.
98. P. Zisman, M. Gutman, and Y. Roizin, Vt drift of Cycled Two-Bit microFlash® Cells, SSDM- 2003, Tokyo, 226-229, 2003.
99. R. Daniel, Y. Shaham-Diamant, and Y. Roizin, Interface states in cycled hot electron injection program/hot electron erase SONOS memories, Applied Physics Letters, 85, 6266-6269 (2004).
100. Y. Roizin, E. Pikhay, and M. Gutman, Suppression of the erased state Vt drift in two-bit per cell SONOS memories, IEEE ED Letters, 26, 35-37 (2005).
101. Jong oh Kim, Non-volatile memory transistor array implementing 'H' shaped source/drain regions and method for fabricating the same, US Patent 6,765,259, 2004.
102. J. Willer, C. Ludwig, J. Deppe, C. Kleint, S. Riedel, J.-U. Sachse, M. Krause, R. Mikalo, E. Stein, V. Kamienski, S. Parascandola, T. Mikolajick, J.-M. Fischer, M. Isler, K-H. Kuesters, I. Bloom, A. Shapir, E. Lusky, and B. Eitan, 110 nm NROM Technology for Code and Data Flash Products, VLSI 2004 Technology Digest, 76-77 (2004).
103. Y. Roizin, A. Heiman, E. Pikhay, M. Lisiansky, E. Aloni, E. Alon, and A. Fenigstein, Extending NROM retention to more than 107 cycles, IEEE NVM Workshop, Monterey, 74-75 (2006).
104. V.A. Gritsenko, K.A. Nasyrov, Yu. N. Novikov, A.L. Aseev, S.Y. Yoon, J.-W. Lee, E.-H. Lee, and C.W. Kim, A new low voltage fast SONOS memory with high-k dielectric, Solid-State Electronics, 47, 1651-1656 (2003).
105. A. Halliyal, M. Ramsbey, W. Zhang, M. Randolph, and F. Cheung, Use of high-k dielectric in modified ONO structure for semiconductor device, US Patent 6,642,573, 2003.
106. 2-based dielectric stacks: internal photoemission measurements, Microelectronic Engineering, 59, 335-339 (2001).
107. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, 'High-K/Metal-Gate Stack and Its MOSFET Characteristics,' IEEE Electron Device Letters, 25(6), 408-410 (2004).
108. J. Van Houdt, High-k materials for nonvolatile memory application, Proceedings IRPS 2005, San Jose, CA, 2005.
109. Y.N. Tan, W.K. Chim, W.K. Choi, M.S. Joo, T.H. Ng, and B.J. Cho, High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation, IEDM Technical Digest, 889-891 (2004).