Ultrashort SONOS memories

IEEE Transactions on Nanotechnology

Volumn 3, Issue 4, 2004, Pages 417-424

  Kim, Moon Kyung ^a,b   Chae, S D ^b   Chae, H S ^b   Kim, J H ^b   Jeong, Y S ^b   Lee, Jo Won ^b   Silva, H ^a   Tiwari, Sandip ^a   Kim, Chung Woo ^b  

^a Cornell University   (United States)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

CMOS device scaling; Nonvolatile memory; Scaling limits; Silicon on insulator (SOI) technology; Silicon oxide nitride oxide silicon (SONOS) memory

Indexed keywords

DEFECTS; ELECTRIC CHARGE; ELECTRON BEAMS; LITHOGRAPHY; NANOSTRUCTURED MATERIALS; NITRIDES; PARAMETER ESTIMATION; SILICON ON INSULATOR TECHNOLOGY;

CMOS DEVICE SCALING; NONVOLATILE MEMORY; SCALING LIMITS; SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORY;

CMOS INTEGRATED CIRCUITS;

EID: 10944247953     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.834161     Document Type: Article

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