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Volumn , Issue , 2005, Pages 234-239

High-k materials for nonvolatile memory applications

Author keywords

Engineered barrier; Flash memory; High k materials; Nonvolatile memory

Indexed keywords

ENGINEERED BARRIERS; HIGH-K MATERIALS; INTERPOLY DIELECTRICS (IPD); NONVOLATILE MEMORY;

EID: 28744456880     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (34)

References (24)
  • 3
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    • VARIOT: A novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices
    • February
    • B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, K. De Meyer, "VARIOT: A novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices", IEEE Electron Device Lett., vol.24, no.2, February 2003, pp.99-101.
    • (2003) IEEE Electron Device Lett. , vol.24 , Issue.2 , pp. 99-101
    • Govoreanu, B.1    Blomme, P.2    Rosmeulen, M.3    Van Houdt, J.4    De Meyer, K.5
  • 4
    • 0000090297 scopus 로고
    • Layered tunnel barriers for nonvolatile memory devices
    • Oct.
    • K.K. Likharev, "Layered tunnel barriers for nonvolatile memory devices", Applied Physics Lett., vol. 73, Oct. 1988, pp.2137-2139.
    • (1988) Applied Physics Lett. , vol.73 , pp. 2137-2139
    • Likharev, K.K.1
  • 5
    • 28744438721 scopus 로고    scopus 로고
    • "Insulating barrier, NVM bandgap design", US patent nr. 6,784,484, Aug.
    • P. Blomme, B. Govoreanu, M. Rosmeulen, "Insulating barrier, NVM bandgap design", US patent nr. 6,784,484, Aug. 2004.
    • (2004)
    • Blomme, P.1    Govoreanu, B.2    Rosmeulen, M.3
  • 9
    • 28744445270 scopus 로고    scopus 로고
    • "Transistor structure for erasable and programmable semiconductor memory devices", US patent nr. 5,583,811, Dec.
    • J. Van Houdt, G. Groeseneken, H.E. Maes, "Transistor structure for erasable and programmable semiconductor memory devices", US patent nr. 5,583,811, Dec. 1996.
    • (1996)
    • Van Houdt, J.1    Groeseneken, G.2    Maes, H.E.3
  • 10
    • 28744454277 scopus 로고    scopus 로고
    • "Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications", US patent nr. 6,246,612, June
    • J. Van Houdt, D. Wellekens, "Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications", US patent nr. 6,246,612, June 2001.
    • (2001)
    • Van Houdt, J.1    Wellekens, D.2
  • 12
    • 4544272065 scopus 로고    scopus 로고
    • The HIMOS Flash technology: The alternative solution for low-cost embedded memory
    • April
    • J. Van Houdt, D. Wellekens, L. Haspeslagh, "The HIMOS Flash technology: the alternative solution for low-cost embedded memory", in Proceedings of the IEEE, vol.91, no.4, April 2003, pp.627-635.
    • (2003) Proceedings of the IEEE , vol.91 , Issue.4 , pp. 627-635
    • Van Houdt, J.1    Wellekens, D.2    Haspeslagh, L.3
  • 17
    • 11144235303 scopus 로고    scopus 로고
    • An overview of logic architectures inside Flash memory devices
    • April
    • A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, and S. Zanardi, "An overview of logic architectures inside Flash memory devices", in Proc. of the IEEE, vol.91, April 2003, pp.569-580.
    • (2003) Proc. of the IEEE , vol.91 , pp. 569-580
    • Silvagni, A.1    Fusillo, G.2    Ravasio, R.3    Picca, M.4    Zanardi, S.5
  • 19
    • 21644433491 scopus 로고    scopus 로고
    • A novel 2-bit/cell nitride storage Flash memory with greater than 1M P/E-cycle endurance
    • Y.-H. Shih, H.-T. Lue, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, "A novel 2-bit/cell nitride storage Flash memory with greater than 1M P/E-cycle endurance", in IEDM Tech. Dig., 2004, pp.881-884.
    • (2004) IEDM Tech. Dig. , pp. 881-884
    • Shih, Y.-H.1    Lue, H.-T.2    Hsieh, K.-Y.3    Liu, R.4    Lu, C.-Y.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.