Performance and reliability Features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

IEEE Transactions on Device and Materials Reliability

Volumn 4, Issue 3, 2004, Pages 377-387

  De Salvo, Barbara ^a   Gerardi, Cosimo ^b   Van Schaijk, Rob ^c   Lombardo, Salvatore A ^d   Corso, Domenico ^d   Plantamura, Cristina ^b   Serafino, Stella ^b   Ammendola, Giuseppe ^b   Van Duuren, Michiel ^c   Goarin, Pierre ^c   Mei, Wan Yuet ^e   Van Jeugd, Kees Der ^e   Baron, Thierry ^f   Gély, Marc ^a   Mur, Pierre ^a   Deleonibus, Simon ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (Italy)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d CNR   (Italy)

^e ASM   (Belgium)

^f CNRS   (France)

Author keywords

Flash; Nonvolatile memories (NVMs); Reliability; Silicon nanocrystals; SONOS

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON TRAPS; LEAKAGE CURRENTS; NANOSTRUCTURED MATERIALS; RELIABILITY; SEMICONDUCTOR MATERIALS; SILICA; SILICON;

FLASH DEVICES; NONVOLATILE MEMORIES (NVM); SILICON NANOCRYSTALS; SONOS;

FLASH MEMORY;

EID: 19944410470     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2004.837209     Document Type: Review

References (63)

1. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to Flash memories," Proc. IEEE, vol. 91, pp. 489-502, Apr. 2003.
2. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells - An overview," Proc. IEEE, vol. 85, pp. 1248-1271, Aug. 1997.
3. J. D. Le, S.-H. Hur, and J.-D. Choi, "Effects of the floating-gate interferences on NAND Flash memory cell operation," IEEE Electron Device Lett., vol. 23, p. 264, 2003.
4. H. Maes and J. F. Van Houdt, "Silicon scaling and its consequences for memory technology," in Proc. IEEE NVSMW, 2003, p. 7.
5. M. van Duuren, R. van Schaijk, N. Akil, W. Baks, P. Goarin, M. Slotboom, P. G. Tello, F. Widdershoven, and N. Wils, "Compact poly-CMP embedded flash memory cells for one and two bit storage," in Proc. IEEE NVSMW, 2003, p. 73.
6. S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, "Volatile and nonvolatile memories with nano-crystal storage," in IEDM Tech. Dig.,1995, p.521.
7. I. De Blauwe, "A novel aerosol nanocrystal floating-gate me device for nonvolatile memory application," in IEDM Tech. Dig., 2000, p. 683.
8. T. Ishii et al., "Engineering variations: Toward practical single-electron (few-electron) memory," in IEDM Tech. Dig., 2000, p. 305.
9. R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parkers, S. G. H. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, K.-M. Chang, and B. E. White Jr., "A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory," in IEDM Tech. Dig., 2003, pp. 601-604.
10. B. De Salvo et al., "How far will silicon nanocrystal push the scaling limits of NVM's technology?," in IEDM Tech. Dig., 2003, p. 597.
11. S. Lombarde, R. A. Puglisi, I. Crupi, D. Corso, G. Nicotra, L. Perniola, B. DeSalvo, and C. Gerardi, "Distribution of the threshold voltage window in nanocrystal memories with Si dots formed by chemical vapor deposition: Effect of partial self-ordering," in Proc. IEEE NVSMW'04, 2004, pp. 69-70.
12. J. DeBlauwe, "Nanocrystal nonvolatile memory devices," IEEE Trans. Nanotechnol., vol. 1, pp. 72-78, Mar. 2002.
13. C. Gerardi, G. Ammendola, M. Melanotte, S. Lombarde, and I. Crupi, "Reliability and retention study of nanocrystal cell arrays," in Proc. 32nd Eur. Solid-State Device Research Conf., ESSDERC 2002, Sept. 2002, p. 475.
14. S. Lombardo, C. Gerardi, D. Corso, G. Ammendola, I. Crupi, and M. Melanotte, "Effects of the distributed charge storage in nanocrystal memory cells," in Proc. IEEE NVSMW, 2003.
15. G. Ammendola, M. Vulpio, M. Bileci, N. Nastasi, C. Gerardi, G. Renna, I. Crupi, G. Nicotra, and S. Lombarde, "Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals," J. Vac. Sci. Technol., vol. B20, p. 2075, 2002.
16. G. Nicotra, R. A. Puglisi, S. Lombardo, C. Spinella, M. Vulpio, G. Ammendola, M. Bileci, and C. Gerardi, "Nucleation kinetics of Si quantum dots on SiO2," J. Appl. Phys, vol. 95, p. 2049, 2004.
17. Y.-S. Yim et al., "70 nm NAND Flash technology with 0.025/spl mu/m/sup 2/ cell size for 4 Gb Flash memory," in IEDM Tech. Dig., 2003, p. 819.
18. C. M. Compagnoni, D. Ielmini, A. S. Spinelli, A. L. Lacaita, C. Previtali, and C. Gerardi, "Study of data retention for nanocrystal Flash memories," in Proc. IEEE Int. Reliability Physics Symp. (IRPS), Dallas, TX, Mar. 30-Apr. 4 2003, pp. 506-512.
19. P. Cappelletti and A. Modelli, "Flash memory reliability," in Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds. Boston, MA: Kluwer, 1999, p. 399.
20. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, "Room temperature single-electron memory using fine-grain polycrystalline silicon," in IEDM Tech. Dig., 1993, p. 541.
21. H. Hanafi, S. Tiwari, and I. Khan, "Fast and long retention time nanocrystal memory," IEEE Trans. Electron Devices, vol. 43, pp. 1553-1558, Sept. 1996.
22. L. Guo, L. Zhuang, and S. Y. Chou, J. Vac. Sci. Technol., vol. 15(B), p. 2840, Nov./Dec. 1997.
23. I. Kim, S. Han, H. Kim, J. Lee, B. Choi, S. Hwang, D. Ahn, and H. Shin, "Room, temperature single effects in Si quantum dot memory with oxide-nitride tunneling dielectrics," in IEDM Tech. Dig., 1998, pp. 111-114.
24. Y. King et al., "A long-refresh dynamic/quasi nonvolatile memory device with 2 nm tunneling oxide," IEEE Electron Device Lett., vol. 20, pp. 409-411, Aug. 1999.
25. B. J. Hinds, K. Nishiguchi, A. Dutta, T. Yamanaka, S. Hatanani, and S. Oda, Jpn. J. Appl. Phys., vol. 39, no. 7B, p. 198, 2000.
26. B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandas, and B. Guillaumot, "Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices," IEEE Trans. Electron Devices, vol. 48, pp. 1789-1799, Aug. 2001.
27. 3 tunneling dielectrics," in IEDM Tech. Dig., Dec. 2001. p. 155.
28. Y. C. King et al., "Charge-trap memory device fabricated by oxidation of Sil -xGex," IEEE Trans. Electron Devices, vol. 48, pp. 696-700, Apr. 2001.
29. J. Koga, R. Ohba, K. Uchida, and A. Toriumi, "Silicon single electron memory and logic devices for room temperature operation," in IEDM Tech. Dig., 2001. pp. 143-146.
30. K. Yano et al., "Nano-structured memories: From technology innovation to value innovation," presented at the Silicon Nanoelectronics Workshop 2001, Kyoto, Japan, 2001.
31. E. Spitale, D. Corso, I. Crupi, G. Nicotra, S. Lombardo, D. Deleruyelle, M. Gely, N. Buffet, B. DeSalvo, and C. Gerardi, "Effect of high-k materials in the control dielectric stack of nanocrystal memories," presented at the ESSDERC, 2004.
32. S. Baik, S. Choi, U. I. Chung, and J. T. Moon, "High speed and non volatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier," in IEDM Tech. Dig., 2003, p. 545.
33. R. A. Rao, R. F. Steimle, M. Sadd, C. T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S. G. H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E. J. Prinz, B. E. White Jr., and R. Muralidhar, "Silicon nanocrystal based memory devices for NVM and DRAM applications," Solid State Electron., vol. 48, pp. 1463-1473, 2004.
34. S. J. Baik, S. Choi, U. I. Chung, and J. T. Moon, "Engineering of tunnel barrier and dot surface in Is nanocrystal memories," Solid State Electron., vol. 48, pp. 1475-1481, 2004.
35. G. Ammendola, V. Ancarani, V. Trioli, M. Bileci, D. Corso, I. Crupi, L. Perniola, C. Gerardi, S. Lombardo, and B. De Salvo, "Nanocrystal memories for Flash device applications," Solid State Electron., vol. 48, pp. 1483-1488, 2004.
36. H. A. R. Wegener et al., "The variable threshold transistor, a new electrically alterable, non destructive read-only-storage device," in IEDM Tech. Dig., Oct. 1967.
37. B. V. Kashvan et al., "MONOS memory element." in IEDM Tech. Dig., Oct. 1968, p. 140.
38. A. Goda and M. Noguchi, "Improvement of erase saturation for highly reliable MONOS memory cell." in Proc. IEEE NVSMW, 2003, pp. 65-68.
39. B. Eitan, "Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping," U.S. Patent 5,768,192, June 16, 1998.
40. B. Eitan et al., "Can NROM, a 2 bit, trapping storage NVM cell, give a real challenge to FG cells?," in Ext. Abst. 1999 Conf. Solid State Devices and Materials, Tokyo, Japan, 1999, p. 522.
41. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
42. E. J. Prinz, G. L. Chindalore, K. Harber, C. M. Hong, C. B. Li, and C. T. Swift. "An embedded 90 nm SUNOS Flash EEPROM utilizing hot electron injection programming and 2-sided hot hole injection erase," in Proc. IEEE NVSMW, 2003, pp. 56-57.
43. R. van Schaijk. M. van Duuren, W. Y. Mei, K. van der Jeugd, A. Rothschild, and M. Demand, "Oxide-nitride-oxide layer optimisation for reliable embedded SONOS memories," Microelectron. Eng., vol. 72, p. 395, 2004.
44. R. van Schaijk, M. van Duuren, P. Goarin, W. Y. Mei, and K. van der Jeugd, "Reliability of embedded SONOS memories," in Proc. ESSDERC, 2004, pp. 277-280.
45. K. Nomoto, I. Fujiwara, H. Aozasa, T. Terano, and T. Kobayashi, "Analytical model of the programming characteristics of scaled MONOS memories with a variety of trap densities and a proposal of a trap-density modulated MONS memory." in IEDM Tech. Dig., 2001, pp. 607-610.
46. M. Tanaka, S. Saida, Y. Mitani, I. Mizushima, and Y. Tsunashima, "Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps," in IEDM Tech. Dig., 2002, pp. 237-240.
47. K. Nomoto, G. Asayama, and T. Kobayashi, "Data retention improvement of MONOS memories by using silicon tetrachloride based silicon nitride with ultra low Si-H bond density," in Ext. Abst. 2003 Conf. Solid State Devices and Materials, 2003, p. 210.
48. Y. K. Lee, S. K. Sung, J. S. Sim, C. J. Lee, T. H. Kim, S. H. Lee, J. K. Lee, B. G. Park, D. H. Lee, and Y. W. Kim, "Multi level vertical channel SONOS nonvolatile memory on SOI," in Symp. VLSI Circuits Tech. Dig., 2002. p. 212.
49. H. Bachhofer, H. Reisinger, E. Bertagnolli, and H. von Philipsborn, "Transient conduction in multidielectric silicon-oxide-nitride-oxide semiconductor structures," J. Appl. Phys., vol. 89, p. 2791, 2001.
50. M. van Duuren, C. de Graaf, R. D. J. Verhaar, G. J. M. Dormans, and F. Widdershoven, "Reliability of extrinsic cells in non-volatile floating gate memories," in Proc. IEEE NVSMW, 2000, p. 99.
51. S.-K. Sung, I.-H. Park, C. J. Lee, Y. K. Lee, J. D. Lee, B.-G. Park, S. D. Chae, and C. W. Kim, "Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices," IEEE Trans. Nanotechnol., vol. 2, pp. 258-264, Dec. 2003.
52. I. Fujiwara et al., "0.13 μm MONOS single transistor memory cell with separated source lines," in IEDM Tech. Dig., 1998, pp. 995-999.
53. F. R. Libsch and M. H. White, "SONOS nonvolatile memories," in Nonvolatile Semiconductor Memory Technologies, W. D. Brown and J. E. Brewer, Eds. New York: IEEE Press, 1998, pp. 309-357.
54. I. Fujiwara et al., "MONOS memory cell scalable to 0.1 μm abd beyond," in Proc. NVSM Workshop, Monterey, CA, 2000, p. 117.
55. M. K. Cho and D. M. Kim, "High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology," IEEE Electron Device Lett., vol. 21, pp. 399-401, Aug. 2000.
56. S. Minami et al., "A 3 volt 1 Mbit full-featured EEPROM using a highly-reliable MONOS device technology," IEICE Trans. Electron., vol. E-776C, pp. 1260-1269, 1994.
57. J. Bloom et al., "NROM - A new non volatile memory technology: From device to products," in Proc. INFOS, 2001, p. 89.
58. L. Lancaster, "Why SONOS," in Proc. NVSM Workshop, 2001, pp. 24-26.
59. Y. Kamigaki and S. Minami, "MNOS nonvolatile semiconductor memory technology: present and future," IEICE Trans. Electron., vol. E84C, p. 713, 2001.
60. C. H. Lee, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, "A Novel SONOS structue of SiO2/SiN/Al203 with TaN metal gate for multi giga bit flash memories," in IEDM Tech. Dig., 2003.
61. J. Buckley, B. DeSalvo, G. Ghibaudo, M. Gely, J. F. Damlencourt, A. M. Papon, X. Garros, and S. Deleonibus, "Engineering of conduction-band- crested barrier or dielectric constant - Crested barrier in view of their application to floating-gate nonvolatile memory devices," in Proc. IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2004.
62. C. Gerardi, S. Lombarde, B. DeSalvo, V. Ancarani, D. Corso, G. Ammendola, G. Nicotra, D. Deleruyelle, M. Melanotte, E. Rimini, and S. Deleonibus, "Fast and low voltage program/erase in nanocrystal memories: Impact of control dielectric optimization," presented at the 20th IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA. Aug. 2004.
63. C. Monzio-Compagnoni, D. lelmini, A. S. Spinelli, A. L. Lacatita, C. Gerardi. and S. Lombarde, "Statistical analysis of nanocrystal memory reliability," presented at the Int. Reliability Physics Symp., Phoenix, AZ, Apr. 2004, p. Paper 9A.1.