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Volumn , Issue , 2012, Pages 329-334

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CIRCUIT STRUCTURES; LOCAL STATE; LOW VOLTAGE CIRCUITS; LOW VOLTAGE OPERATION; LOW-POWER CONSUMPTION; LOW-VOLTAGE APPLICATIONS; MEMRISTOR; NON-VOLATILE; POWER FAILURE; RELIABLE OPERATION; RESISTIVE MEMORIES; WRITE SPEED;

EID: 84859951825     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2012.6164968     Document Type: Conference Paper
Times cited : (39)

References (76)
  • 1
    • 0034315851 scopus 로고    scopus 로고
    • A Dynamic Voltage Scaled Microprocessor System
    • Nov.
    • T. D. Burd, et al., "A Dynamic Voltage Scaled Microprocessor System," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.11 , pp. 1571-1580
    • Burd, T.D.1
  • 2
    • 0036858657 scopus 로고    scopus 로고
    • A 32-bit PowerPC System-on-a-Chip with Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling
    • Nov.
    • K. J. Nowka, et al., "A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.11 , pp. 1441-1447
    • Nowka, K.J.1
  • 3
    • 22544455956 scopus 로고    scopus 로고
    • Joint Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Read-Time Embedded Systems
    • July
    • L. Yan, J. Luo, and N. K. Jha, "Joint Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Read-Time Embedded Systems," IEEE J. Solid-State Circuits, vol. 24, no. 7, pp. 1030-1041, July 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.24 , Issue.7 , pp. 1030-1041
    • Yan, L.1    Luo, J.2    Jha, N.K.3
  • 4
    • 70449473258 scopus 로고    scopus 로고
    • A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
    • Nov.
    • M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3163-3173, Nov. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.44 , Issue.11 , pp. 3163-3173
    • Sinangil, M.E.1    Verma, N.2    Chandrakasan, A.P.3
  • 5
    • 69449085255 scopus 로고    scopus 로고
    • Wide VDD Embedded Asynchronous SRAM with Dual-Mode Self-Timed Technique for Dynamic Voltage Systems
    • Aug.
    • M.-F. Chang, S.-M. Yang, and K.-T. Chen, "Wide VDD Embedded Asynchronous SRAM with Dual-Mode Self-Timed Technique for Dynamic Voltage Systems," IEEE Trans. Circuits Syst. I, vol. 56, no. 8, pp. 1657-1667, Aug. 2009.
    • (2009) IEEE Trans. Circuits Syst. I , vol.56 , Issue.8 , pp. 1657-1667
    • Chang, M.-F.1    Yang, S.-M.2    Chen, K.-T.3
  • 6
    • 37749046808 scopus 로고    scopus 로고
    • An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment
    • Y. Morita, et al., "An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2007, pp. 256-257.
    • IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2007 , pp. 256-257
    • Morita, Y.1
  • 7
    • 77953243784 scopus 로고    scopus 로고
    • A differential data-aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications
    • June
    • M.-F. Chang, et al., "A differential data-aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1234-1245, June 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.6 , pp. 1234-1245
    • Chang, M.-F.1
  • 8
    • 79953214888 scopus 로고    scopus 로고
    • A large σVTH/VDD tolerant ZigZag 8T SRAM with area-Efficient decoupled differential sensing and fast write-back scheme
    • April
    • J.-J. Wu, et al., "A large σVTH/VDD tolerant ZigZag 8T SRAM with area-Efficient decoupled differential sensing and fast write-back scheme," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 815-827, April 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.4 , pp. 815-827
    • Wu, J.-J.1
  • 9
    • 84860875993 scopus 로고    scopus 로고
    • Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)
    • Oct.
    • M.-F. Chang, et al., "Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)," The IEEE 9th International Conference on ASIC (ASICON), pp. 327-330, Oct. 2011
    • (2011) The IEEE 9th International Conference on ASIC (ASICON) , pp. 327-330
    • Chang, M.-F.1
  • 10
    • 77957980630 scopus 로고    scopus 로고
    • A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications
    • June
    • P.-F. Chiu, M.-F. Chang, et al., "A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 229-230, June 2010.
    • (2010) Symposium on VLSI Circuits Dig. Tech. Papers , pp. 229-230
    • Chiu, P.-F.1    Chang, M.-F.2
  • 12
    • 84859991243 scopus 로고    scopus 로고
    • Challenges and Trends of Resistive Memory (Memristor) Based Circuits for 3D-IC Applications
    • Sep.
    • M.-F. Chang, et al., "Challenges and Trends of Resistive Memory (Memristor) Based Circuits for 3D-IC Applications,"2011 Symposium on Solid State Devices and Materials (SSDM), pp. 1053-1054, Sep. 2011.
    • (2011) 2011 Symposium on Solid State Devices and Materials (SSDM) , pp. 1053-1054
    • Chang, M.-F.1
  • 14
    • 67349182866 scopus 로고    scopus 로고
    • Phase-change-driven programmable switch for nonvolatile logic applications
    • S.-M. Yoon, et al., "Phase-change-driven programmable switch for nonvolatile logic applications," IEEE Electron Device Letters, vol. 30, no. 4, pp.371-373, 2009
    • (2009) IEEE Electron Device Letters , vol.30 , Issue.4 , pp. 371-373
    • Yoon, S.-M.1
  • 15
    • 0015127532 scopus 로고
    • Memristor-the missing circuit element
    • Sept.
    • Leon O. Chua, "Memristor-the missing circuit element," IEEE Tran. Circuit Theory, vol. ct-18, no. 5, pp.507-519, Sept. 1971
    • (1971) IEEE Tran. Circuit Theory , vol.CT-18 , Issue.5 , pp. 507-519
    • Chua, L.O.1
  • 16
    • 33847722993 scopus 로고    scopus 로고
    • Non-volatile Resistive Switching for Advanced Memory Applications
    • A. Chen, et al., "Non-volatile Resistive Switching for Advanced Memory Applications," IEDM, pp.746-749, 2005.
    • (2005) IEDM , pp. 746-749
    • Chen, A.1
  • 17
    • 79951826963 scopus 로고    scopus 로고
    • Electron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis
    • Dec.
    • Y. H. Tseng, et al., "Electron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis, " IEDM, pp. 28.5.1-28.5.4, Dec. 2010
    • (2010) IEDM
    • Tseng, Y.H.1
  • 18
    • 50249156872 scopus 로고    scopus 로고
    • Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V
    • Dec.
    • K. Tsunoda, et al., "Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V," IEDM, pp. 767-770, Dec. 2007
    • (2007) IEDM , pp. 767-770
    • Tsunoda, K.1
  • 19
    • 43049126833 scopus 로고    scopus 로고
    • The missing memristor found
    • May
    • Dmitri B. Strukov, et al., "The missing memristor found,"Nature, issue 453, pp. 80-83, May 2008.
    • (2008) Nature , Issue.453 , pp. 80-83
    • Strukov, D.B.1
  • 20
    • 67949097936 scopus 로고    scopus 로고
    • 2Based RRAM
    • Dec.
    • 2Based RRAM," IEDM, pp. 1-4, Dec. 2008.
    • (2008) IEDM , pp. 1-4
    • Lee, H.Y.1
  • 21
    • 68249128656 scopus 로고    scopus 로고
    • Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism
    • Dec.
    • Z. Wei, et al., "Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism," IEDM, pp. 293-296, Dec. 2008
    • (2008) IEDM , pp. 293-296
    • Wei, Z.1
  • 22
    • 79955442181 scopus 로고    scopus 로고
    • A Forming-free Wox Resistive Memory Using a Novel Self-aligned Field Enhancement Feature with Excellent Reliability and Scalability
    • Dec.
    • W.C. Chien, et al., "A Forming-free Wox Resistive Memory Using a Novel Self-aligned Field Enhancement Feature with Excellent Reliability and Scalability," IEDM, pp. 440-443, Dec. 2010
    • (2010) IEDM , pp. 440-443
    • Chien, W.C.1
  • 23
    • 77957923289 scopus 로고    scopus 로고
    • CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array
    • May
    • S. Kawabata, et al., "CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array," in Proc. the International Memory Workshop (IMW), pp. 1-2, May 2010
    • (2010) Proc. the International Memory Workshop (IMW) , pp. 1-2
    • Kawabata, S.1
  • 24
    • 79960837152 scopus 로고    scopus 로고
    • Low Power Operating Bipolar TMO ReRAM for Sub 10 nm Era
    • Dec.
    • M. J. Kim, et al., "Low Power Operating Bipolar TMO ReRAM for Sub 10 nm Era," IEDM, pp. 444-447, Dec. 2010
    • (2010) IEDM , pp. 444-447
    • Kim, M.J.1
  • 25
    • 80052683906 scopus 로고    scopus 로고
    • Forming-Free Nitrogen-Doped AlO X RRAM with Sub-μA Programming Current
    • June
    • Wanki Kim, et al., "Forming-Free Nitrogen-Doped AlO X RRAM with Sub-μA Programming Current," Symposium on VLSI Technology, pp. 22-23, June 2011.
    • (2011) Symposium on VLSI Technology , pp. 22-23
    • Kim, W.1
  • 26
    • 80052662808 scopus 로고    scopus 로고
    • Bi-layered RRAM with Unlimited Endurance and Extremely Uniform Switching
    • June
    • Y.-B. Kim, et al., "Bi-layered RRAM with Unlimited Endurance and Extremely Uniform Switching," Symp. VLSI Circuits Dig. Tech. Papers," pp. 52-53, June 2011.
    • (2011) Symp. VLSI Circuits Dig. Tech. Papers , pp. 52-53
    • Kim, Y.-B.1
  • 27
    • 79951833149 scopus 로고    scopus 로고
    • Evidence and solution of over-RESET problem for HfOx based resistive memory with sub-ns switching speed and high endurance
    • Dec.
    • H. Lee, et al., "Evidence and solution of over-RESET problem for HfOx based resistive memory with sub-ns switching speed and high endurance," IEDM, pp. 19.7.1 - 19.7.4, Dec. 2010
    • (2010) IEDM
    • Lee, H.1
  • 28
    • 79951564013 scopus 로고    scopus 로고
    • Fast Access Speed RRAM for Embedded Applications
    • Jan.
    • S.-S. Sheu*, K.-H. Cheng, M.-F. Chang, et al., "Fast Access Speed RRAM for Embedded Applications," IEEE Design and Test of Computers, vol. 28. no. 1, pp. 64-71, Jan. 2011.
    • (2011) IEEE Design and Test of Computers , vol.28 , Issue.1 , pp. 64-71
    • Sheu, S.-S.1    Cheng, K.-H.2    Chang, M.-F.3
  • 29
  • 31
    • 68549087135 scopus 로고    scopus 로고
    • Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs
    • Aug.
    • N. Sakimura, T. Sugibayashi, R. Nebashi, and N. Kasai, "Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs,"IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2244-2250, Aug. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.8 , pp. 2244-2250
    • Sakimura, N.1    Sugibayashi, T.2    Nebashi, R.3    Kasai, N.4
  • 32
    • 0035273822 scopus 로고    scopus 로고
    • NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors
    • Mar.
    • T. Miwa, et al., "NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 522-527, Mar. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.3 , pp. 522-527
    • Miwa, T.1
  • 36
    • 0023437909 scopus 로고
    • Static-noise margin analysis of MOS SRAM cells
    • Oct.
    • E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp.748-754, Oct. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.22 , Issue.5 , pp. 748-754
    • Seevinck, E.1    List, F.J.2    Lohstroh, J.3
  • 37
    • 25144518593 scopus 로고    scopus 로고
    • Process variation in embedded memories:Failure analysis and variation aware architecture
    • Sep.
    • A. Agarwal, B. C. Paul, S. Mukhopadhyay, and K. Roy, "Process variation in embedded memories:failure analysis and variation aware architecture," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp.1804-1814, Sep. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.9 , pp. 1804-1814
    • Agarwal, A.1    Paul, B.C.2    Mukhopadhyay, S.3    Roy, K.4
  • 38
    • 33746369469 scopus 로고    scopus 로고
    • Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    • July
    • B. H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673 - 1679, July 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.7 , pp. 1673-1679
    • Calhoun, B.H.1    Chandrakasan, A.P.2
  • 39
    • 79551573138 scopus 로고    scopus 로고
    • A 130 mV SRAM with Expanded Write and Read Margins for Subthreshold Applications
    • Feb.
    • M.-F. Chang, S.-W. Chang, P.-W. Chou, and W.-C. Wu, "A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 520-529, Feb. 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.2 , pp. 520-529
    • Chang, M.-F.1    Chang, S.-W.2    Chou, P.-W.3    Wu, W.-C.4
  • 41
    • 31344451652 scopus 로고    scopus 로고
    • A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
    • Jan.
    • K. Zhang, et al., "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.1 , pp. 146-151
    • Zhang, K.1
  • 42
    • 39749201604 scopus 로고    scopus 로고
    • An SRAM design in 65nm and 45nm technology nodes featuring read and write-assist circuits to expand operating voltage
    • June
    • H. Pilo, et al., "An SRAM design in 65nm and 45nm technology nodes featuring read and write-assist circuits to expand operating voltage, " Symp. VLSI Circuits Dig. Tech. Papers, pp. 15-16, June 2006.
    • (2006) Symp. VLSI Circuits Dig. Tech. Papers , pp. 15-16
    • Pilo, H.1
  • 43
    • 85008042429 scopus 로고    scopus 로고
    • A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations
    • Jan.
    • K. Nii, et al., "A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations,"IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 180-191, Jan. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.1 , pp. 180-191
    • Nii, K.1
  • 44
    • 33947613119 scopus 로고    scopus 로고
    • A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits
    • April
    • S. Ohbayashi, et al. "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 820-829, April 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.4 , pp. 820-829
    • Ohbayashi, S.1
  • 45
    • 49549090007 scopus 로고    scopus 로고
    • A 100nm double-stacked 500Mhz 72Mb separate-I/O synchronous SRAM with automatic cell-bias scheme and adaptive block redundancy
    • Feb.
    • K. Sohn, et al., "A 100nm double-stacked 500Mhz 72Mb separate-I/O synchronous SRAM with automatic cell-bias scheme and adaptive block redundancy," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 386-622, Feb. 2008.
    • (2008) IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers , pp. 386-622
    • Sohn, K.1
  • 46
    • 70349271250 scopus 로고    scopus 로고
    • A process-variation-tolerant dual-power-supply SRAM with 0.179μm2 cell in 40nm CMOS using level-programmable wordline driver
    • Feb.
    • O. Hirabayashi, et al., "A process-variation-tolerant dual-power-supply SRAM with 0.179μm2 cell in 40nm CMOS using level-programmable wordline driver," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 458-459, Feb. 2009.
    • (2009) IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers , pp. 458-459
    • Hirabayashi, O.1
  • 47
    • 39749136138 scopus 로고    scopus 로고
    • A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
    • June
    • A. Bhavnagarwala, et al., "A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing," Symp. VLSI Circuits Dig. Tech. Papers, pp. 78-79, June 2007.
    • (2007) Symp. VLSI Circuits Dig. Tech. Papers , pp. 78-79
    • Bhavnagarwala, A.1
  • 48
    • 52249106671 scopus 로고    scopus 로고
    • A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses
    • Sept.
    • T. Suzuki, et al., "A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2109-2119, Sept. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.9 , pp. 2109-2119
    • Suzuki, T.1
  • 49
    • 34548858947 scopus 로고    scopus 로고
    • A 65nm 8T subthreshold SRAM employing sense-amplifier redundancy
    • Feb.
    • N. Verma and A. P. Chandrakasan, "A 65nm 8T subthreshold SRAM employing sense-amplifier redundancy", ISSCC Dig. Tech. Papers, pp. 328-606, Feb. 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 328-606
    • Verma, N.1    Chandrakasan, A.P.2
  • 51
    • 51949088226 scopus 로고    scopus 로고
    • A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD-min VLSIs
    • June
    • Y. H. Chen, et al., "A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD-min VLSIs, " Symp. VLSI Circuits Dig. Tech. Papers, pp. 210-211, June 2008.
    • (2008) Symp. VLSI Circuits Dig. Tech. Papers , pp. 210-211
    • Chen, Y.H.1
  • 54
    • 34548845553 scopus 로고    scopus 로고
    • Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V
    • Feb.
    • J. Pille, et al., "Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 322-606, Feb. 2007.
    • (2007) IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers , pp. 322-606
    • Pille, J.1
  • 55
    • 2942659548 scopus 로고    scopus 로고
    • 0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme
    • June
    • M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V logic-library- friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 934-940, June 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.6 , pp. 934-940
    • Yamaoka, M.1    Osada, K.2    Ishibashi, K.3
  • 56
    • 34548274890 scopus 로고    scopus 로고
    • On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology
    • Sept.
    • F.-S. Lai and C.-F. Lee, "On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2061-2070, Sept. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.9 , pp. 2061-2070
    • Lai, F.-S.1    Lee, C.-F.2
  • 57
    • 33644653243 scopus 로고    scopus 로고
    • A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - Sure write operation by using step-down negatively overdriven bitline scheme
    • March
    • N. Shibata, et al., "A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 728-742, March 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.3 , pp. 728-742
    • Shibata, N.1
  • 58
    • 33846259499 scopus 로고    scopus 로고
    • Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs
    • June
    • M. Khellah, et al., "Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs," Symp. VLSI Circuits Dig. Tech. Papers, pp. 9-10, June 2006.
    • (2006) Symp. VLSI Circuits Dig. Tech. Papers , pp. 9-10
    • Khellah, M.1
  • 59
    • 63449132966 scopus 로고    scopus 로고
    • A 0.7V single-supply SRAM with 0.495umP2P cell in 65nm Technology utilizing self-write-back sense amplifier and cascaded bit line scheme
    • April
    • K. Kushida, et al., "A 0.7V single-supply SRAM with 0.495umP2P cell in 65nm Technology utilizing self-write-back sense amplifier and cascaded bit line scheme," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1192-1198, April 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.4 , pp. 1192-1198
    • Kushida, K.1
  • 60
    • 31344473488 scopus 로고    scopus 로고
    • A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications
    • Jan.
    • K. Takeda, et al., "A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-121, Jan. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.1 , pp. 113-121
    • Takeda, K.1
  • 61
    • 33644640188 scopus 로고    scopus 로고
    • Stable SRAM Cell Design for the 32 nm Node and Beyond
    • June
    • L. Chang, et al., "Stable SRAM Cell Design for the 32 nm Node and Beyond" Symp. VLSI Technology. Dig. Tech. Papers, pp. 128-129, June 2005.
    • (2005) Symp. VLSI Technology. Dig. Tech. Papers , pp. 128-129
    • Chang, L.1
  • 64
    • 39749154813 scopus 로고    scopus 로고
    • 6.6+GHz low Vmin, read and half select disturb-free 1.2Mb SRAM
    • June
    • R. Joshi, et al., "6.6+GHz low Vmin, read and half select disturb-free 1.2Mb SRAM," Symp. VLSI Circuits Dig. Tech. Papers, pp. 250-251, June 2007.
    • (2007) Symp. VLSI Circuits Dig. Tech. Papers , pp. 250-251
    • Joshi, R.1
  • 65
    • 41549129905 scopus 로고    scopus 로고
    • An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
    • April
    • L. Chang, et al., "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," IEEE J. Solid-State Circuits, vol. 43, no.4, pp. 956-963, April, 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 956-963
    • Chang, L.1
  • 66
    • 67649651691 scopus 로고    scopus 로고
    • A voltage scalable 0.26V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode
    • T.-H. Kim, J. Liu, and C. H. Kim, "A voltage scalable 0.26V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785-1795, 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.6 , pp. 1785-1795
    • Kim, T.-H.1    Liu, J.2    Kim, C.H.3
  • 67
  • 68
    • 47649109815 scopus 로고    scopus 로고
    • A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using Symmetrized 9T SRAM cell with controlled read
    • Jan.
    • S. A. Verkila, S. K. Bondada, and B. S. Amrutur, "A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using Symmetrized 9T SRAM cell with controlled read," in Proc. Conference on VLSI Design, pp. 560-565, Jan. 2008.
    • (2008) Proc. Conference on VLSI Design , pp. 560-565
    • Verkila, S.A.1    Bondada, S.K.2    Amrutur, B.S.3
  • 72
    • 34748830993 scopus 로고    scopus 로고
    • A 160mV robust schmitt trigger based subthreshold SRAM
    • Oct.
    • J. P. Kulkarni, K. Kim, and K. Roy, "A 160mV robust schmitt trigger based subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.10 , pp. 2303-2313
    • Kulkarni, J.P.1    Kim, K.2    Roy, K.3
  • 73
    • 33749524067 scopus 로고    scopus 로고
    • An ultra-low-power memory with a subthreshold power supply voltage
    • Oct.
    • J. Chen, L. T. Clark, and T.-H. Chen, "An ultra-low-power memory with a subthreshold power supply voltage," IEEE J. Solid-State Circuits, vol. 41 no. 10, pp.2344-2353, Oct. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.10 , pp. 2344-2353
    • Chen, J.1    Clark, L.T.2    Chen, T.-H.3
  • 74
    • 49549116677 scopus 로고    scopus 로고
    • A single-power-supply 0.7V 1GHz 45nm SRAM with an asymmetrical unit-β-ratio memory Cell
    • Feb.
    • A. Kawasumi, et al., "A single-power-supply 0.7V 1GHz 45nm SRAM with an asymmetrical unit-β-ratio memory Cell," ISSCC Dig. Tech. Papers, pp. 382-622, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 382-622
    • Kawasumi, A.1
  • 76
    • 84859949446 scopus 로고    scopus 로고
    • M.S. thesis, Institute of Electronics Engineering, National Tsing Hua Univ., Hsinchu, Taiwan, May
    • L.-F. Chen, "A 7T SRAM Circuit Design for Low Voltage Applications," M.S. thesis, Institute of Electronics Engineering, National Tsing Hua Univ., Hsinchu, Taiwan, May 2011.
    • (2011) A 7T SRAM Circuit Design for Low Voltage Applications
    • Chen, L.-F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.