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Volumn 51, Issue , 2008, Pages 382-622

A single-power-supply 0.7V 1GHz 45nm SRAM with an asymmetrical unit-β-ratio memory cell

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

EID: 49549116677     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523217     Document Type: Conference Paper
Times cited : (34)

References (8)
  • 2
    • 39749191416 scopus 로고    scopus 로고
    • A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses
    • Jun
    • T. Suzuki, H. Yamauchi, Y. Yamagami et al., "A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses," Dig. Symp. VLSI Circuits, pp. 14-15, Jun. 2006.
    • (2006) Dig. Symp. VLSI Circuits , pp. 14-15
    • Suzuki, T.1    Yamauchi, H.2    Yamagami, Y.3
  • 3
    • 39749175133 scopus 로고    scopus 로고
    • A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
    • Jun
    • S. Ohbayashi, M. Yabuuchi, K. Nii et al., "A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits," Dig. Symp. VLSI Circuits, pp. 20-21, Jun. 2006.
    • (2006) Dig. Symp. VLSI Circuits , pp. 20-21
    • Ohbayashi, S.1    Yabuuchi, M.2    Nii, K.3
  • 4
    • 33947623051 scopus 로고    scopus 로고
    • A 5.6GHz 64kB Dual-Read Data Cache for the POWER6™ Processor
    • Feb
    • J. Davis, D. Plass, P. Bunce et al., "A 5.6GHz 64kB Dual-Read Data Cache for the POWER6™ Processor," ISSCC Dig. Tech. Papers, pp. 622-623, Feb. 2006.
    • (2006) ISSCC Dig. Tech. Papers , pp. 622-623
    • Davis, J.1    Plass, D.2    Bunce, P.3
  • 5
    • 37749013850 scopus 로고    scopus 로고
    • A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
    • Jun
    • L. Chang, Y Nakamura, R. Montoye et al., "A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS,"Dig. Symp. VLSI Circuits, pp. 252-253, Jun. 2007.
    • (2007) Dig. Symp. VLSI Circuits , pp. 252-253
    • Chang, L.1    Nakamura, Y.2    Montoye, R.3
  • 6
    • 34548845553 scopus 로고    scopus 로고
    • Implementation of the CELL Broadband Engine™ in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V
    • Feb
    • J. Pille, C. Adams, T. Christensen et al., "Implementation of the CELL Broadband Engine™ in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V," ISSCC Dig. Tech. Papers, pp. 322-323, Feb. 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 322-323
    • Pille, J.1    Adams, C.2    Christensen, T.3
  • 7
    • 39749154813 scopus 로고    scopus 로고
    • 6.6+ GHz Low Vmin, read and half select disturb-free 1.2Mb SRAM
    • Jun
    • R. Joshi, R. Houle, K. Batson et al., "6.6+ GHz Low Vmin, read and half select disturb-free 1.2Mb SRAM," Dig. Symp. VLSI Circuits, pp. 250-251, Jun. 2007.
    • (2007) Dig. Symp. VLSI Circuits , pp. 250-251
    • Joshi, R.1    Houle, R.2    Batson, K.3
  • 8
    • 39749107272 scopus 로고    scopus 로고
    • Effect of Power Supply Noise on SRAM Dynamic Stability
    • Jun
    • M. Khellah, D. Khalil, D. Somasekhar et al., "Effect of Power Supply Noise on SRAM Dynamic Stability," Dig. Symp. VLSI Circuits, pp. 76-77, Jun. 2007.
    • (2007) Dig. Symp. VLSI Circuits , pp. 76-77
    • Khellah, M.1    Khalil, D.2    Somasekhar, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.