A 100nm double-stacked 500MHz 72Mb separate-I/O synchronous SRAM with automatic cell-bias scheme and adaptive block redundancy

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 386-622

  Sohn, Kyomin ^a   Suh, Young Ho ^a   Son, Young Jae ^a   Yim, Dae Sik ^a   Kim, Kang Young ^a   Bae, Dae Gi ^a   Kang, Ted ^a   Lim, Hoon ^a   Jung, Soon Moon ^a   Byun, Hyun Geun ^a   Jun, Young Hyun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CYTOLOGY; REDUNDANCY;

BLOCK REDUNDANCY; CELL TRANSISTOR; CONTROL CHARACTERISTICS; OPERATING FREQUENCY; PULSEWIDTHS; SRAM CELL; WORDLINES;

CELLS;

EID: 49549090007     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523219     Document Type: Conference Paper

References (4)

1. Y. Suh, H. Nam, S. Kang et al., "A 256Mb Synchronous-Burst DDR SRAM with Hierarchical Bit-Line Architecture for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 476-477, Feb. 2005.
2. S. Jung, H. Lim, C. Yeo et al., "High Speed and Highly Cost Effective 72M bit Density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory," Dig. Symp. VLSI Technology, pp. 82-83, Jun. 2007.
3. H. Yu, N. Kim, Y. Son et al., "A SRAM Core Architecture with Adaptive Cell Bias Scheme," Dig. Symp. VLSI Circuit, pp. 128-129, Jun. 2006.
4. H. Sakakibara, M. Nakayama, M. Kusunoki et al., "A 750MHz 144Mb Cache DRAM LSI with Speed Scalable Design and Programmable At-Speed Function-Array BIST," ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2003.