A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 9, 2008, Pages 2109-2119

  Suzuki, Toshikazu ^b   Yamauchi, Hiroyuki ^a,c   Yamagami, Yoshinobu ^b   Satomi, Katsuji ^b   Akamatsu, Hironori ^b  

^a IEEE

^b PANASONIC CORPORATION   (Japan)

^c FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

2 port; Cell current; Embedded SRAM; Memory cell; Stability

Indexed keywords

CMOS INTEGRATED CIRCUITS; CYTOLOGY; PORTS AND HARBORS; RANDOM PROCESSES; SPECTRUM ANALYZERS; STATIC RANDOM ACCESS STORAGE;

2-PORT; A-STABLE; AREA PENALTY; BIASING TECHNIQUES; BIT LINES; CELL CURRENTS; CELL DESIGN; CELL SIZES; CELL-CURRENT; CMOS TECHNOLOGIES; DUAL-VDD; EMBEDDED SRAM; MEMORY CELL; RANDOM FLUCTUATIONS; SRAM CELLS; STABILITY; STATIC-NOISE MARGIN;

CELLS;

EID: 52249106671     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2001872     Document Type: Article

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