Process variation in embedded memories: Failure analysis and variation aware architecture

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 9, 2005, Pages 1804-1813

  Agarwal, Amit ^a   Paul, Bipul C ^a   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Resizing; SRAM failures; Variation aware cache; Yield

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; SOLID STATE DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS;

RESIZING; SRAM FAILURES; VARIATION AWARE CACHE; YIELD;

FAILURE ANALYSIS;

EID: 25144518593     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.852159     Document Type: Conference Paper

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