Techniques for leakage energy reduction in deep submicrometer cache memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 11, 2006, Pages 1238-1248

  Frustaci, Fabio ^b   Corsonello, Pasquale ^a,b   Perri, Stefania ^a,b   Cocorullo, Giuseppe ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF CALABRIA   (Italy)

Author keywords

Cache memories; CMOS memory integrated circuits; Low power memories

Indexed keywords

CMOS MEMORY INTEGRATED CIRCUITS; LEAKAGE ENERGY REDUCTION; LOW POWER MEMORIES;

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; STANDBY POWER SYSTEMS; STATIC RANDOM ACCESS STORAGE;

LEAKAGE CURRENTS;

EID: 33845530240     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.886397     Document Type: Article

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