A 0.7 V single-supply SRAM with 0.495 μm2cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1192-1198

  Kushida, Keiichi ^a   Suzuki, Azuma ^a   Fukano, Gou ^a   Kawasumi, Atsushi ^a   Hirabayashi, Osamu ^a   Takeyama, Yasuhisa ^a   Sasaki, Takahiko ^a   Katayama, Akira ^a   Fujimura, Yuki ^a   Yabe, Tomoaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Divided bit line; Low power design; SRAM; Ultra highdensity cell

Indexed keywords

CMOS INTEGRATED CIRCUITS;

65NM CMOS TECHNOLOGIES; 65NM TECHNOLOGIES; BIT LINES; DIVIDED BIT LINE; FAILURE RATES; HIERARCHICAL BIT LINES; LOW-POWER DESIGN; ORDERS OF MAGNITUDES; PROCESS COSTS; SENSE AMPLIFIERS; SINGLE-SUPPLY OPERATIONS; SRAM; TEST CHIPS; ULTRA-HIGHDENSITY CELL; VOLTAGE OPERATIONS; WRITE BACKS;

STATIC RANDOM ACCESS STORAGE;

EID: 63449132966     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014009     Document Type: Conference Paper

References (14)

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