A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 820-829

  Ohbayashi, Shigeki ^b   Yabuuchi, Makoto ^b   Nil, Koji ^a,b   Tsukamoto, Yasumasa ^b   Imaoka, Susumu ^c   Oda, Yuji ^d   Yoshihara, Tsutomu ^a,e   Igarashi, Motoshige ^b   Takeuchi, Masahiko ^b   Kawashima, Hiroshi ^b   Yamaguchi, Yasuo ^b   Tsukamoto, Kazuhiro ^b   Inuishi, Masahide ^b   Makino, Hiroshi ^b   Ishibashi, Koichiro ^a,b   Shinohara, Hirofumi ^b  

^a IEEE

^b RENESAS TECHNOLOGY CORP   (Japan)

^c Renesas Design Corporation   (Japan)

^d Shikino High Tech Corporation   (Japan)

^e WASEDA UNIVERSITY   (Japan)

Author keywords

65 nm CMOS; 6T SRAM; Assist circuit; CMOS; Embedded SRAM; SRAM; Vth curve; Vth variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; STANDBY POWER SYSTEMS;

ASSIST CIRCUITS; EMBEDDED SRAM; LOW STAND-BY POWER (LSTP);

STATIC RANDOM ACCESS STORAGE;

EID: 33947613119     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.891648     Document Type: Article

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